Merge pull request #750 from YosysHQ/gatecat/io-improve

IO improvements for OBUFTDS

common/router2.cc

@@ -856,13 +856,23 @@ struct Router2
                                   int(a.first), int(a.second), ctx->nameOf(net));
                     auto res2 = route_arc(t, net, a.first, a.second, is_mt, false);
                     // If this also fails, no choice but to give up
-                    if (res2 != ARC_SUCCESS)
+                    if (res2 != ARC_SUCCESS) {
+                        if (ctx->debug) {
+                            log_info("Pre-bound routing: \n");
+                            for (auto &wire_pair : net->wires) {
+                                log("        %s", ctx->nameOfWire(wire_pair.first));
+                                if (wire_pair.second.pip != PipId())
+                                    log(" %s", ctx->nameOfPip(wire_pair.second.pip));
+                                log("\n");
+                            }
+                        }
                         log_error("Failed to route arc %d.%d of net '%s', from %s to %s.\n", int(a.first),
                                   int(a.second), ctx->nameOf(net), ctx->nameOfWire(ctx->getNetinfoSourceWire(net)),
                                   ctx->nameOfWire(ctx->getNetinfoSinkWire(net, net->users.at(a.first), a.second)));
                     }
                 }
             }
+        }
         if (cfg.perf_profile) {
             auto rend = std::chrono::high_resolution_clock::now();
             nets.at(net->udata).total_route_us +=
@@ -968,18 +978,18 @@ struct Router2
                 log_error("Internal error; incomplete route tree for arc %d of net %s.\n", usr_idx, ctx->nameOf(net));
             }
             auto &p = wd.bound_nets.at(net->udata).second;
-            if (!ctx->checkPipAvail(p)) {
+            if (ctx->checkPipAvailForNet(p, net)) {
                 NetInfo *bound_net = ctx->getBoundPipNet(p);
-                if (bound_net != net) {
+                if (bound_net == nullptr) {
+                    to_bind.push_back(p);
+                }
+            } else {
                 if (ctx->verbose) {
                     log_info("Failed to bind pip %s to net %s\n", ctx->nameOfPip(p), net->name.c_str(ctx));
                 }
                 success = false;
                 break;
             }
-            } else {
-                to_bind.push_back(p);
-            }
             cursor = ctx->getPipSrcWire(p);
         }
 

fpga_interchange/arch.cc

@@ -1518,11 +1518,6 @@ void Arch::remove_pip_pseudo_wires(PipId pip, NetInfo *net)
             // This wire is part of net->wires, make sure it has no pip,
             // but leave it alone.  It will get cleaned up via
             // unbindWire.
-            if (wire_iter->second.pip != PipId() && wire_iter->second.pip != pip) {
-                log_error("Wire %s report source'd from pip %s, which is not %s\n", nameOfWire(wire),
-                          nameOfPip(wire_iter->second.pip), nameOfPip(pip));
-            }
-            NPNR_ASSERT(wire_iter->second.pip == PipId() || wire_iter->second.pip == pip);
         } else {
             // This wire is not in net->wires, update wire_to_net.
 #ifdef DEBUG_BINDING
@@ -1756,12 +1751,12 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
         NPNR_ASSERT(src != wire);
         NPNR_ASSERT(dst != wire);
 
-        NetInfo *net = getConflictingWireNet(wire);
+        NetInfo *other_net = getConflictingWireNet(wire);
-        if (net != nullptr) {
+        if (other_net != nullptr && other_net != net) {
 #ifdef DEBUG_BINDING
             if (getCtx()->verbose) {
                 log_info("Pip %s is not available because wire %s is tied to net %s\n", getCtx()->nameOfPip(pip),
-                         getCtx()->nameOfWire(wire), net->name.c_str(getCtx()));
+                         getCtx()->nameOfWire(wire), other_net->name.c_str(getCtx()));
             }
 #endif
             return false;

fpga_interchange/arch.h

@@ -576,6 +576,7 @@ struct Arch : ArchAPI<ArchRanges>
         const PipInfoPOD &pip_data = pip_info(chip_info, pip);
         for (int32_t wire_index : pip_data.pseudo_cell_wires) {
             wire.index = wire_index;
+            if (getBoundWireNet(wire) != net)
                 assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true);
         }
 
@@ -708,7 +709,8 @@ struct Arch : ArchAPI<ArchRanges>
 
     // -------------------------------------------------
 
-    void place_iobufs(WireId pad_wire, NetInfo *net, const pool<CellInfo *, hash_ptr_ops> &tightly_attached_bels,
+    void place_iobufs(WireId pad_wire, NetInfo *net,
+                      const dict<CellInfo *, IdString, hash_ptr_ops> &tightly_attached_bels,
                       pool<CellInfo *, hash_ptr_ops> *placed_cells);
 
     void pack_ports();

fpga_interchange/arch_pack_io.cc

@@ -27,7 +27,7 @@
 NEXTPNR_NAMESPACE_BEGIN
 
 namespace {
-bool search_routing_for_placement(Arch *arch, WireId start_wire, CellInfo *cell, IdString cell_pin)
+bool search_routing_for_placement(Arch *arch, WireId start_wire, CellInfo *cell, IdString cell_pin, bool downhill)
 {
     std::queue<WireId> visit_queue;
     pool<WireId> already_visited;
@@ -51,54 +51,44 @@ bool search_routing_for_placement(Arch *arch, WireId start_wire, CellInfo *cell,
             // Bel pin doesn't match
             arch->unbindBel(bp.bel);
         }
-        for (auto pip : arch->getPipsDownhill(next)) {
+        auto do_visit = [&](PipId pip) {
-            WireId dst = arch->getPipDstWire(pip);
+            WireId dst = downhill ? arch->getPipDstWire(pip) : arch->getPipSrcWire(pip);
             if (already_visited.count(dst))
-                continue;
+                return;
             if (!arch->is_site_wire(dst) && arch->get_wire_category(dst) == WIRE_CAT_GENERAL)
-                continue; // this pass only considers dedicated routing
+                return; // this pass only considers dedicated routing
             visit_queue.push(dst);
             already_visited.insert(dst);
+        };
+        if (downhill) {
+            for (auto pip : arch->getPipsDownhill(next))
+                do_visit(pip);
+        } else {
+            for (auto pip : arch->getPipsUphill(next))
+                do_visit(pip);
         }
     }
     return false;
 }
 } // namespace
 
-void Arch::place_iobufs(WireId pad_wire, NetInfo *net, const pool<CellInfo *, hash_ptr_ops> &tightly_attached_bels,
+void Arch::place_iobufs(WireId pad_wire, NetInfo *net,
+                        const dict<CellInfo *, IdString, hash_ptr_ops> &tightly_attached_bels,
                         pool<CellInfo *, hash_ptr_ops> *placed_cells)
 {
-    for (BelPin bel_pin : getWireBelPins(pad_wire)) {
+    Context *ctx = getCtx();
-        BelId bel = bel_pin.bel;
+    for (auto cell_port : tightly_attached_bels) {
-        for (CellInfo *cell : tightly_attached_bels) {
+        bool downhill = (cell_port.first->ports.at(cell_port.second).type != PORT_OUT);
-            if (isValidBelForCellType(cell->type, bel)) {
+        if (search_routing_for_placement(this, pad_wire, cell_port.first, cell_port.second, downhill)) {
-                NPNR_ASSERT(cell->bel == BelId());
+            if (ctx->verbose)
-                NPNR_ASSERT(placed_cells->count(cell) == 0);
+                log_info("Placed IO cell %s:%s at %s.\n", ctx->nameOf(cell_port.first),
-
+                         ctx->nameOf(cell_port.first->type), ctx->nameOfBel(cell_port.first->bel));
-                bindBel(bel, cell, STRENGTH_FIXED);
-                placed_cells->emplace(cell);
-
-                IdString cell_port;
-                for (auto pin_pair : cell->cell_bel_pins) {
-                    for (IdString a_bel_pin : pin_pair.second) {
-                        if (a_bel_pin == bel_pin.pin) {
-                            NPNR_ASSERT(cell_port == IdString());
-                            cell_port = pin_pair.first;
-                        }
-                    }
-                }
-                NPNR_ASSERT(cell_port != IdString());
-
-                const PortInfo &port = cell->ports.at(cell_port);
-                NPNR_ASSERT(port.net == net);
-            }
         }
     }
 
     // Also try, on a best-effort basis, to preplace other cells in the macro based on downstream routing. This is
     // needed for the split INBUF+IBUFCTRL arrangement in the UltraScale+, as just placing the INBUF will result in an
     // unrouteable site and illegal placement.
-    Context *ctx = getCtx();
     std::queue<CellInfo *> place_queue;
     for (auto pc : *placed_cells)
         place_queue.push(pc);
@@ -119,7 +109,7 @@ void Arch::place_iobufs(WireId pad_wire, NetInfo *net, const pool<CellInfo *, ha
                 if (usr.cell->bel != BelId() || usr.cell->macro_parent != cursor->macro_parent)
                     continue;
                 // Try and place using dedicated routing
-                if (search_routing_for_placement(this, src_wire, usr.cell, usr.port)) {
+                if (search_routing_for_placement(this, src_wire, usr.cell, usr.port, true)) {
                     // Successful
                     placed_cells->insert(usr.cell);
                     place_queue.push(usr.cell);
@@ -200,34 +190,34 @@ void Arch::pack_ports()
     for (auto port_pair : port_cells) {
         IdString port_name = port_pair.first;
         CellInfo *port_cell = port_pair.second;
-        pool<CellInfo *, hash_ptr_ops> tightly_attached_bels;
+        dict<CellInfo *, IdString, hash_ptr_ops> tightly_attached_bels;
 
         for (auto port_pair : port_cell->ports) {
             const PortInfo &port_info = port_pair.second;
             const NetInfo *net = port_info.net;
             if (net->driver.cell) {
-                tightly_attached_bels.emplace(net->driver.cell);
+                tightly_attached_bels.emplace(net->driver.cell, net->driver.port);
             }
 
             for (const PortRef &port_ref : net->users) {
                 if (port_ref.cell) {
-                    tightly_attached_bels.emplace(port_ref.cell);
+                    tightly_attached_bels.emplace(port_ref.cell, port_ref.port);
                 }
             }
         }
 
         if (getCtx()->verbose) {
             log_info("Tightly attached BELs for port %s\n", port_name.c_str(getCtx()));
-            for (CellInfo *cell : tightly_attached_bels) {
+            for (auto cell_port : tightly_attached_bels) {
-                log_info(" - %s : %s\n", cell->name.c_str(getCtx()), cell->type.c_str(getCtx()));
+                log_info(" - %s : %s\n", cell_port.first->name.c_str(getCtx()), cell_port.first->type.c_str(getCtx()));
             }
         }
 
         NPNR_ASSERT(tightly_attached_bels.erase(port_cell) == 1);
         pool<IdString> cell_types_in_io_group;
-        for (CellInfo *cell : tightly_attached_bels) {
+        for (auto cell_port : tightly_attached_bels) {
-            NPNR_ASSERT(port_cells.find(cell->name) == port_cells.end());
+            NPNR_ASSERT(port_cells.find(cell_port.first->name) == port_cells.end());
-            cell_types_in_io_group.emplace(cell->type);
+            cell_types_in_io_group.emplace(cell_port.first->type);
         }
 
         // Get possible placement locations for tightly coupled BELs with

fpga_interchange/examples/tests/CMakeLists.txt

@@ -6,4 +6,5 @@ add_subdirectory(ff)
 add_subdirectory(lut)
 add_subdirectory(lut_nexus)
 add_subdirectory(lutram)
+add_subdirectory(obuftds)
 add_subdirectory(ram_nexus)

fpga_interchange/examples/tests/obuftds/CMakeLists.txt

@@ -0,0 +1,7 @@
+add_interchange_group_test(
+    name obuftds
+    family ${family}
+    board_list basys3
+    tcl run.tcl
+    sources obuftds.v
+)

fpga_interchange/examples/tests/obuftds/basys3.xdc

@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN V2 [get_ports sw[8] ]
+set_property PACKAGE_PIN T3 [get_ports sw[9] ]
+set_property PACKAGE_PIN T2 [get_ports sw[10]]
+set_property PACKAGE_PIN R3 [get_ports sw[11]]
+
+set_property PACKAGE_PIN U19 [get_ports diff_p[0]]
+set_property PACKAGE_PIN V19 [get_ports diff_n[0]]
+set_property PACKAGE_PIN V13 [get_ports diff_p[1]]
+set_property PACKAGE_PIN V14 [get_ports diff_n[1]]

fpga_interchange/examples/tests/obuftds/obuftds.v

@@ -0,0 +1,37 @@
+module top(
+  input  wire [11:8] sw,
+
+  output wire [1:0]  diff_p,
+  output wire [1:0]  diff_n
+);
+
+wire [1:0] buf_i;
+wire [1:0] buf_t;
+
+OBUFTDS # (
+  .IOSTANDARD("DIFF_SSTL135"),
+  .SLEW("FAST")
+) obuftds_0 (
+  .I(buf_i[0]),
+  .T(buf_t[0]),
+  .O(diff_p[0]),
+  .OB(diff_n[0])
+);
+
+OBUFTDS # (
+  .IOSTANDARD("DIFF_SSTL135"),
+  .SLEW("FAST")
+) obuftds_1 (
+  .I(buf_i[1]),
+  .T(buf_t[1]),
+  .O(diff_p[1]),
+  .OB(diff_n[1])
+);
+
+assign buf_i[0] = sw[ 8];
+assign buf_t[0] = sw[ 9];
+assign buf_i[1] = sw[10];
+assign buf_t[1] = sw[11];
+
+endmodule
+

fpga_interchange/examples/tests/obuftds/run.tcl

@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)

fpga_interchange/macros.cc

@@ -58,14 +58,24 @@ void Arch::expand_macros()
 
     std::vector<CellInfo *> next_cells;
 
+    bool first_iter = false;
     do {
         // Expand cells
         for (auto cell : cells) {
             // TODO: consult exception map
             const MacroExpansionPOD *exp = lookup_macro_rules(chip_info, cell->type);
+
+            // Block infinite expansion loop due to a macro being expanded in the same primitive.
+            // E.g.: OBUFTDS expands into the following cells, with an infinite loop being generated:
+            //          - 2 OBUFTDS
+            //          - 1 INV
+            if (exp && first_iter)
+                continue;
+
             const MacroPOD *macro = lookup_macro(chip_info, exp ? IdString(exp->macro_name) : cell->type);
             if (macro == nullptr)
                 continue;
+
             // Get the ultimate root of this macro expansion
             IdString parent = (cell->macro_parent == IdString()) ? cell->name : cell->macro_parent;
             // Create child instances
@@ -158,6 +168,8 @@ void Arch::expand_macros()
         // The next iteration only needs to look at cells created in this iteration
         std::swap(next_cells, cells);
         next_cells.clear();
+
+        first_iter = true;
     } while (!cells.empty());
     // Do this at the end, otherwise we might add cells that are later destroyed
     for (auto &cell : ctx->cells)