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place_sa: Improvements including supporting force and ordering consistency

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-20 20:12:23 +02:00
parent c515e5da2d
commit c27c96f4f0
3 changed files with 20 additions and 12 deletions
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24
common/place_sa.cc
View File

@ -145,7 +145,7 @@ class SAPlacer
curr_wirelength = 0; curr_wirelength = 0;
for (auto net : ctx->nets) { for (auto net : ctx->nets) {
float wl = get_wirelength(net.second); float wl = get_wirelength(net.second);
wirelengths[net.second] = wl; wirelengths[net.first] = wl;
curr_wirelength += wl; curr_wirelength += wl;
} }
@ -221,9 +221,17 @@ class SAPlacer
std::string cell_text = "no cell"; std::string cell_text = "no cell";
if (cell != IdString()) if (cell != IdString())
cell_text = std::string("cell '") + cell.str(ctx) + "'"; cell_text = std::string("cell '") + cell.str(ctx) + "'";
log_error("post-placement validity check failed for Bel '%s' " if (ctx->force) {
"(%s)", log_warning(
ctx->getBelName(bel).c_str(ctx), cell_text.c_str()); "post-placement validity check failed for Bel '%s' "
"(%s)\n",
ctx->getBelName(bel).c_str(ctx), cell_text.c_str());
} else {
log_error(
"post-placement validity check failed for Bel '%s' "
"(%s)\n",
ctx->getBelName(bel).c_str(ctx), cell_text.c_str());
}
} }
} }
return true; return true;
@ -328,7 +336,7 @@ class SAPlacer
bool try_swap_position(CellInfo *cell, BelId newBel) bool try_swap_position(CellInfo *cell, BelId newBel)
{ {
static std::unordered_set<NetInfo *> update; static std::unordered_set<NetInfo *> update;
static std::vector<std::pair<NetInfo *, float>> new_lengths; static std::vector<std::pair<IdString, float>> new_lengths;
new_lengths.clear(); new_lengths.clear();
update.clear(); update.clear();
BelId oldBel = cell->bel; BelId oldBel = cell->bel;
@ -373,10 +381,10 @@ class SAPlacer
// Recalculate wirelengths for all nets touched by the peturbation // Recalculate wirelengths for all nets touched by the peturbation
for (auto net : update) { for (auto net : update) {
new_wirelength -= wirelengths.at(net); new_wirelength -= wirelengths.at(net->name);
float net_new_wl = get_wirelength(net); float net_new_wl = get_wirelength(net);
new_wirelength += net_new_wl; new_wirelength += net_new_wl;
new_lengths.push_back(std::make_pair(net, net_new_wl)); new_lengths.push_back(std::make_pair(net->name, net_new_wl));
} }
delta = new_wirelength - curr_wirelength; delta = new_wirelength - curr_wirelength;
n_move++; n_move++;
@ -434,7 +442,7 @@ class SAPlacer
} }
Context *ctx; Context *ctx;
std::unordered_map<NetInfo *, float> wirelengths; std::unordered_map<IdString, float> wirelengths;
float curr_wirelength = std::numeric_limits<float>::infinity(); float curr_wirelength = std::numeric_limits<float>::infinity();
float temp = 1000; float temp = 1000;
bool improved = false; bool improved = false;

4
ice40/pack.cc
View File

@ -244,8 +244,8 @@ static void set_net_constant(const Context *ctx, NetInfo *orig,
CellInfo *uc = user.cell; CellInfo *uc = user.cell;
log_info("%s user %s\n", orig->name.c_str(ctx), log_info("%s user %s\n", orig->name.c_str(ctx),
uc->name.c_str(ctx)); uc->name.c_str(ctx));
if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I') && if ((is_lut(ctx, uc) || is_lc(ctx, uc)) &&
!constval) { (user.port.str(ctx).at(0) == 'I') && !constval) {
uc->ports[user.port].net = nullptr; uc->ports[user.port].net = nullptr;
} else { } else {
uc->ports[user.port].net = constnet; uc->ports[user.port].net = constnet;

4
ice40/picorv32_arachne.sh
View File

@ -3,7 +3,7 @@ set -ex
rm -f picorv32.v rm -f picorv32.v
wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v
arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif -o picorv32_arachne_all.asc
yosys -p "read_blif -wideports picorv32_place.blif; read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json" yosys -p "read_blif -wideports picorv32_place.blif; read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json"
./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json ./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json
../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32_place_nx.json ../nextpnr-ice40 --hx8k --asc picorv32_ar_placed.asc --json picorv32_place_nx.json --force