cyclonev: Add enough stubs that it links

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-01 13:40:45 +01:00
parent 9901a5fafc
commit c3cb9aa3f6
4 changed files with 147 additions and 28 deletions

View File

@ -38,7 +38,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
Arch::Arch(ArchArgs args)
{
this->args = args;
this->cyclonev = mistral::CycloneV::get_model(args.device);
this->cyclonev = mistral::CycloneV::get_model(args.device, args.mistral_root);
NPNR_ASSERT(this->cyclonev != nullptr);
for (int x = 0; x < cyclonev->get_tile_sx(); x++) {
@ -189,4 +189,23 @@ IdString Arch::getBelType(BelId bel) const
return IdString();
}
bool Arch::pack() { return true; }
bool Arch::place() { return true; }
bool Arch::route() { return true; }
#ifdef WITH_HEAP
const std::string Arch::defaultPlacer = "heap";
#else
const std::string Arch::defaultPlacer = "sa";
#endif
const std::vector<std::string> Arch::availablePlacers = {"sa",
#ifdef WITH_HEAP
"heap"
#endif
};
const std::string Arch::defaultRouter = "router1";
const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
NEXTPNR_NAMESPACE_END

View File

@ -34,6 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
struct ArchArgs
{
std::string device;
std::string mistral_root;
};
struct PinInfo
@ -78,12 +79,12 @@ struct ArchRanges : BaseArchRanges
using TileBelsRangeT = std::vector<BelId>;
using BelPinsRangeT = std::vector<IdString>;
// Wires
using AllWiresRangeT = const std::vector<WireId> &;
using AllWiresRangeT = const std::unordered_set<WireId> &;
using DownhillPipRangeT = const std::vector<PipId> &;
using UphillPipRangeT = const std::vector<PipId> &;
using WireBelPinRangeT = std::vector<BelPin>;
using WireBelPinRangeT = const std::vector<BelPin> &;
// Pips
using AllPipsRangeT = const std::vector<PipId> &;
using AllPipsRangeT = const std::unordered_set<PipId> &;
};
struct Arch : BaseArch<ArchRanges>
@ -95,6 +96,7 @@ struct Arch : BaseArch<ArchRanges>
std::vector<BelId> bel_list;
Arch(ArchArgs args);
ArchArgs archArgs() const { return args; }
std::string getChipName() const override { return std::string{"TODO: getChipName"}; }
// -------------------------------------------------
@ -115,41 +117,41 @@ struct Arch : BaseArch<ArchRanges>
}
BelId getBelByLocation(Loc loc) const override { return BelId(CycloneV::xy2pos(loc.x, loc.y), loc.z); }
IdString getBelType(BelId bel) const override; // arch.cc
WireId getBelPinWire(BelId bel, IdString pin) const override;
PortType getBelPinType(BelId bel, IdString pin) const override;
std::vector<IdString> getBelPins(BelId bel) const override;
WireId getBelPinWire(BelId bel, IdString pin) const override { return WireId(); }
PortType getBelPinType(BelId bel, IdString pin) const override { return PORT_IN; }
std::vector<IdString> getBelPins(BelId bel) const override { return {}; }
// -------------------------------------------------
WireId getWireByName(IdStringList name) const override;
IdStringList getWireName(WireId wire) const override;
DelayQuad getWireDelay(WireId wire) const;
std::vector<BelPin> getWireBelPins(WireId wire) const override;
const std::vector<WireId> &getWires() const override;
WireId getWireByName(IdStringList name) const override { return WireId(); }
IdStringList getWireName(WireId wire) const override { return IdStringList(); }
DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return empty_belpin_list; }
const std::unordered_set<WireId> &getWires() const override { return all_wires; }
// -------------------------------------------------
PipId getPipByName(IdStringList name) const override;
const std::vector<PipId> &getPips() const override;
Loc getPipLocation(PipId pip) const override;
IdStringList getPipName(PipId pip) const override;
PipId getPipByName(IdStringList name) const override { return PipId(); }
const std::unordered_set<PipId> &getPips() const override { return all_pips; }
Loc getPipLocation(PipId pip) const override { return Loc(0, 0, 0); }
IdStringList getPipName(PipId pip) const override { return IdStringList(); }
WireId getPipSrcWire(PipId pip) const override { return WireId(pip.src); };
WireId getPipDstWire(PipId pip) const override { return WireId(pip.dst); };
DelayQuad getPipDelay(PipId pip) const override;
const std::vector<PipId> &getPipsDownhill(WireId wire) const override;
const std::vector<PipId> &getPipsUphill(WireId wire) const override;
DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(0); }
const std::vector<PipId> &getPipsDownhill(WireId wire) const override { return empty_pip_list; }
const std::vector<PipId> &getPipsUphill(WireId wire) const override { return empty_pip_list; }
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const override;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
delay_t getDelayEpsilon() const override;
delay_t getRipupDelayPenalty() const override;
float getDelayNS(delay_t v) const override;
delay_t getDelayFromNS(float ns) const override;
uint32_t getDelayChecksum(delay_t v) const override;
delay_t estimateDelay(WireId src, WireId dst) const override { return 100; };
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override { return 100; };
delay_t getDelayEpsilon() const override { return 10; };
delay_t getRipupDelayPenalty() const override { return 100; };
float getDelayNS(delay_t v) const override { return float(v) / 1000.0f; };
delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000.0f); };
uint32_t getDelayChecksum(delay_t v) const override { return v; };
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override { return ArcBounds(); }
// -------------------------------------------------
@ -163,6 +165,12 @@ struct Arch : BaseArch<ArchRanges>
static const std::vector<std::string> availablePlacers;
static const std::string defaultRouter;
static const std::vector<std::string> availableRouters;
// WIP to link without failure
std::unordered_set<WireId> all_wires;
std::unordered_set<PipId> all_pips;
std::vector<PipId> empty_pip_list;
std::vector<BelPin> empty_belpin_list;
};
NEXTPNR_NAMESPACE_END

View File

@ -1,5 +1,11 @@
set(MISTRAL_ROOT "" CACHE STRING "Mistral install path")
aux_source_directory(${MISTRAL_ROOT}/lib MISTRAL_FILES)
add_library(mistral STATIC ${MISTRAL_FILES})
find_package(LibLZMA REQUIRED)
foreach(family_target ${family_targets})
target_include_directories(${family_target} PRIVATE ${MISTRAL_ROOT}/lib)
target_include_directories(${family_target} PRIVATE ${MISTRAL_ROOT}/lib ${LIBLZMA_INCLUDE_DIRS})
target_link_libraries(${family_target} PRIVATE mistral ${LIBLZMA_LIBRARIES})
endforeach()

86
cyclonev/main.cc Normal file
View File

@ -0,0 +1,86 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2021 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifdef MAIN_EXECUTABLE
#include <fstream>
#include "command.h"
#include "design_utils.h"
#include "jsonwrite.h"
#include "log.h"
#include "timing.h"
USING_NEXTPNR_NAMESPACE
class MistralCommandHandler : public CommandHandler
{
public:
MistralCommandHandler(int argc, char **argv);
virtual ~MistralCommandHandler(){};
std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override;
void setupArchContext(Context *ctx) override{};
void customBitstream(Context *ctx) override;
void customAfterLoad(Context *ctx) override;
protected:
po::options_description getArchOptions() override;
};
MistralCommandHandler::MistralCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
po::options_description MistralCommandHandler::getArchOptions()
{
po::options_description specific("Architecture specific options");
specific.add_options()("mistral", po::value<std::string>(), "path to mistral root");
specific.add_options()("device", po::value<std::string>(), "device name (e.g. 5CSEBA6U23I7)");
return specific;
}
void MistralCommandHandler::customBitstream(Context *ctx)
{
// TODO: rbf gen via mistral
}
std::unique_ptr<Context> MistralCommandHandler::createContext(std::unordered_map<std::string, Property> &values)
{
ArchArgs chipArgs;
if (!vm.count("mistral")) {
log_error("mistral must be specified on the command line\n");
}
if (!vm.count("device")) {
log_error("device must be specified on the command line (e.g. --device 5CSEBA6U23I7)\n");
}
chipArgs.mistral_root = vm["mistral"].as<std::string>();
chipArgs.device = vm["device"].as<std::string>();
auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
return ctx;
}
void MistralCommandHandler::customAfterLoad(Context *ctx)
{
// TODO: qsf parsing
}
int main(int argc, char *argv[])
{
MistralCommandHandler handler(argc, argv);
return handler.exec();
}
#endif