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docs: Tidy up

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-10-01 09:02:29 +01:00
parent 3c7c95ecce
commit c4244d967d
2 changed files with 30 additions and 32 deletions
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4
docs/constraints.md
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@ -13,9 +13,9 @@ and the ECP5 architecture supports a subset of LPF constraints (for details see
LOCATE COMP "led[0]" SITE "E16"; LOCATE COMP "led[0]" SITE "E16";
IOBUF PORT "led[0]" IO_TYPE=LVCMOS25; IOBUF PORT "led[0]" IO_TYPE=LVCMOS25;
IOBUF ... DRIVE=8; IOBUF ... DRIVE=4|8|12|16; // currently LVCMOS33 and LVCMOS33D only
IOBUF ... OPENDRAIN=ON|OFF; IOBUF ... OPENDRAIN=ON|OFF;
IOBUF ... TERMINATION=50; IOBUF ... TERMINATION=50|75|150;
IOBUF ... DIFFRESISTOR=100; //for differential IO only IOBUF ... DIFFRESISTOR=100; //for differential IO only
IOBUF ... CLAMP=ON|OFF; IOBUF ... CLAMP=ON|OFF;
IOBUF ... PULLMODE=UP|DOWN|NONE; IOBUF ... PULLMODE=UP|DOWN|NONE;

58
ecp5/docs/primitives.md
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@ -2,45 +2,43 @@
nextpnr-ecp5 currently supports the following primitives: nextpnr-ecp5 currently supports the following primitives:
- **ALU54B** - 54-bit ternary adder/subtractor for high speed (limited support, must be manually placed) - **ALU54B** - 54-bit ternary adder/subtractor (limited support, must be manually placed)
- **CCU2C** - carry chain - **CCU2C** - 2x LUT4 with carry logic
- **CLKDIVF** - clock divider - **CLKDIVF** - clock divider
- **DCUA** - **DCUA** - dual channel 3/5Gbps SERDES
- **DDRDLLA** - 90° delay for DQS or clock for DDR interface - **DDRDLLA** - 90° delay for DQS or clock for DDR interface
- **DELAYF** - configurable signal delay - **DELAYF** - configurable signal delay
- **DELAYG** - simple signal delay - **DELAYG** - simple signal delay
- **DP16KD** - true dual port block RAM - **DP16KD** - true dual port block RAM
- **DQSBUFM** - DQS circuit for DDR memory - **DQSBUFM** - DQS control for DDR memory
- **DTR** - die temperature readout *notice: The IO-names in the FPGA Libraries Reference Guide 08/16 are wrong* - **DTR** - die temperature readout *notice: The IO-names in the FPGA Libraries Reference Guide 08/16 are wrong*
- **ECLKSYNCB** - external clock stop block for DDR-stuff - **ECLKSYNCB** - edge clock stop/synchronisation
- **EHXPLLL** - global(??) phase-locked-loop - **EHXPLLL** - phase-locked-loop
- **EXTREFB** - reference clock input buffer for external clock for Serdes TxPLL - **EXTREFB** - reference clock input buffer for external clock for SERDES
- **GSR** - global set/reset interface - **GSR** - global set/reset interface
- **IDDR71B** - 7:1 LVDS input - **IDDR71B** - 7:1 input gearbox
- **IDDRX1F** - generic input DDR primitive - **IDDRX1F** - generic 1:2 input DDR
- **IDDRX2DQA** - DDR2/3 memory input interface - **IDDRX2DQA** - DDR2/3 memory 1:4 input interface
- **IDDRX2F** - generic input DDR primitive - **IDDRX2F** - generic 1:4 input DDR
- **IOLOGIC** - **JTAGG** - JTAG access to fabric
- **JTAGG** - access to JTAG controller (untested) - **L6MUX21** - 2 input multiplexer for LUT6 and above
- **L6MUX21** - 2 to 1 multiplexer
- **LUT4** - 4 input Look Up Table - **LUT4** - 4 input Look Up Table
- **MULT18X18D** - DSP multiplier (cascade functionality not supported) - **MULT18X18D** - DSP multiplier (cascade functionality not supported)
- **ODDR71B** - 7:1 LVDS ODDR implementation - **ODDR71B** - 7:1 ODDR implementation
- **ODDRX1F** - generic X1 ODDR implementation - **ODDRX1F** - generic 2:1 output DDR
- **ODDRX2DQA** - memory output DDR primitive for DQ outputs - **ODDRX2DQA** - memory 4:1 output DDR primitive for DQ outputs
- **ODDRX2DQSB** - memory output DDR primitive for DQS outputs - **ODDRX2DQSB** - memory 4:1 output DDR primitive for DQS outputs
- **ODDRX2F** - generic X2 ODDR implementation - **ODDRX2F** - generic 4:1 output DDR
- **OSCG** - access to / control of internal oscillator - **OSCG** - internal oscillator
- **OSHX2A** - memory output DDR primitive for address and command - **OSHX2A** - memory 4:1 output DDR primitive for address and command
- **PCSCLKDIV** - **PCSCLKDIV** - clock divider for SERDES clock outputs
- **PFUMX** - 2 input multiplexer within the programmable function unit (PFU) - **PFUMX** - 2 input multiplexer for LUT5s
- **SEDGA** - allows checking configuration data for soft-errors, see TN1268 (untested) - **SEDGA** - allows checking configuration data for soft-errors, see TN1268 (untested)
- **SIOLOGIC** - **TRELLIS_DPR16X4** - 16x4 LUTRAM
- **TRELLIS_DPR16X4** - **TRELLIS_ECLKBUF** - internal edge clock buffer
- **TRELLIS_ECLKBUF** - **TRELLIS_FF** - SLICE flipflop
- **TRELLIS_FF** - **TRELLIS_IO** - tristate IO, mapped by Yosys from BB, IB, OB, etc
- **TRELLIS_IO** - **TRELLIS_SLICE** - logic SLICE (2x LUT4, 2x FF, 2x MUX2, CCU2 carry)
- **TRELLIS_SLICE**
- **TSHX2DQA** - tristate control for DQ data output for DDR2 and DDR3 memory - **TSHX2DQA** - tristate control for DQ data output for DDR2 and DDR3 memory
- **TSHX2DQSA** - tristate control for DQS output - **TSHX2DQSA** - tristate control for DQS output
- **USRMCLK** - provides access to SPI PROM - **USRMCLK** - provides access to SPI flash clock (MCLK)