Merge pull request #201 from eddiehung/xc7
Remove some more ice40 stuff
This commit is contained in:
Eddie Hung
GitHub
commit
c51d89f2af
34
xc7/arch.cc
34
xc7/arch.cc
@ -442,44 +442,14 @@ BelId Arch::getBelByLocation(Loc loc) const
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
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br.e.cursor = br.b.cursor;
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if (br.e.cursor != -1) {
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while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
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chip_info->bel_data[br.e.cursor].y == y)
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br.e.cursor++;
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}
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NPNR_ASSERT("TODO");
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return br;
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (bel_wires[i].port == pin.index)
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return PortType(bel_wires[i].type);
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}
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} else {
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int b = 0, e = num_bel_wires - 1;
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while (b <= e) {
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int i = (b + e) / 2;
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if (bel_wires[i].port == pin.index)
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return PortType(bel_wires[i].type);
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if (bel_wires[i].port > pin.index)
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e = i - 1;
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else
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b = i + 1;
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}
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}
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NPNR_ASSERT("TODO");
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return PORT_INOUT;
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}
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209
xc7/arch.h
209
xc7/arch.h
@ -64,210 +64,6 @@ template <> struct hash<Arc>
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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int32_t port;
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int32_t type;
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int32_t wire_index;
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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int32_t type;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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int8_t x, y, z;
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int8_t padding_0;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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int32_t bel_index;
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int32_t port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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enum PipFlags : uint32_t
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{
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FLAG_NONE = 0,
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FLAG_ROUTETHRU = 1,
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FLAG_NOCARRY = 2
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};
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// RelPtr<char> name;
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int32_t src, dst;
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int32_t fast_delay;
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int32_t slow_delay;
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int8_t x, y;
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int16_t src_seg, dst_seg;
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int16_t switch_mask;
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int32_t switch_index;
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PipFlags flags;
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});
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NPNR_PACKED_STRUCT(struct WireSegmentPOD {
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int8_t x, y;
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int16_t index;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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enum WireType : int8_t
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{
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WIRE_TYPE_NONE = 0,
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WIRE_TYPE_GLB2LOCAL = 1,
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WIRE_TYPE_GLB_NETWK = 2,
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WIRE_TYPE_LOCAL = 3,
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WIRE_TYPE_LUTFF_IN = 4,
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WIRE_TYPE_LUTFF_IN_LUT = 5,
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WIRE_TYPE_LUTFF_LOUT = 6,
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WIRE_TYPE_LUTFF_OUT = 7,
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WIRE_TYPE_LUTFF_COUT = 8,
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WIRE_TYPE_LUTFF_GLOBAL = 9,
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WIRE_TYPE_CARRY_IN_MUX = 10,
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WIRE_TYPE_SP4_V = 11,
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WIRE_TYPE_SP4_H = 12,
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WIRE_TYPE_SP12_V = 13,
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WIRE_TYPE_SP12_H = 14
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};
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RelPtr<char> name;
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int32_t num_uphill, num_downhill;
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RelPtr<int32_t> pips_uphill, pips_downhill;
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int32_t num_bel_pins;
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RelPtr<BelPortPOD> bel_pins;
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int32_t num_segments;
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RelPtr<WireSegmentPOD> segments;
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int32_t fast_delay;
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int32_t slow_delay;
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int8_t x, y, z;
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WireType type;
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});
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NPNR_PACKED_STRUCT(struct PackagePinPOD {
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RelPtr<char> name;
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int32_t bel_index;
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});
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NPNR_PACKED_STRUCT(struct PackageInfoPOD {
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RelPtr<char> name;
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int32_t num_pins;
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RelPtr<PackagePinPOD> pins;
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});
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enum TileType : uint32_t
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{
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TILE_NONE = 0,
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TILE_LOGIC = 1,
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TILE_IO = 2,
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TILE_RAMB = 3,
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TILE_RAMT = 4,
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TILE_DSP0 = 5,
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TILE_DSP1 = 6,
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TILE_DSP2 = 7,
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TILE_DSP3 = 8,
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TILE_IPCON = 9
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};
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NPNR_PACKED_STRUCT(struct ConfigBitPOD { int8_t row, col; });
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NPNR_PACKED_STRUCT(struct ConfigEntryPOD {
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RelPtr<char> name;
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int32_t num_bits;
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RelPtr<ConfigBitPOD> bits;
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});
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NPNR_PACKED_STRUCT(struct TileInfoPOD {
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int8_t cols, rows;
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int16_t num_config_entries;
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RelPtr<ConfigEntryPOD> entries;
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});
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static const int max_switch_bits = 5;
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NPNR_PACKED_STRUCT(struct SwitchInfoPOD {
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int32_t num_bits;
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int32_t bel;
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int8_t x, y;
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ConfigBitPOD cbits[max_switch_bits];
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});
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NPNR_PACKED_STRUCT(struct IerenInfoPOD {
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int8_t iox, ioy, ioz;
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int8_t ierx, iery, ierz;
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});
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NPNR_PACKED_STRUCT(struct BitstreamInfoPOD {
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int32_t num_switches, num_ierens;
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RelPtr<TileInfoPOD> tiles_nonrouting;
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RelPtr<SwitchInfoPOD> switches;
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RelPtr<IerenInfoPOD> ierens;
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});
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NPNR_PACKED_STRUCT(struct BelConfigEntryPOD {
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RelPtr<char> entry_name;
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RelPtr<char> cbit_name;
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int8_t x, y;
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int16_t padding;
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});
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// Stores mapping between bel parameters and config bits,
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// for extra cells where this mapping is non-trivial
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NPNR_PACKED_STRUCT(struct BelConfigPOD {
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int32_t bel_index;
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int32_t num_entries;
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RelPtr<BelConfigEntryPOD> entries;
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});
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NPNR_PACKED_STRUCT(struct CellPathDelayPOD {
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int32_t from_port;
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int32_t to_port;
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int32_t fast_delay;
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int32_t slow_delay;
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});
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NPNR_PACKED_STRUCT(struct CellTimingPOD {
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int32_t type;
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int32_t num_paths;
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RelPtr<CellPathDelayPOD> path_delays;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_bels, num_wires, num_pips;
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int32_t num_switches, num_belcfgs, num_packages;
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int32_t num_timing_cells;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pip_data;
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RelPtr<TileType> tile_grid;
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RelPtr<BitstreamInfoPOD> bits_info;
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RelPtr<BelConfigPOD> bel_config;
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RelPtr<PackageInfoPOD> packages_data;
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RelPtr<CellTimingPOD> cell_timing;
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});
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struct TorcInfo
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{
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TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName);
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@ -339,8 +135,6 @@ struct TorcInfo
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};
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extern std::unique_ptr<const TorcInfo> torc_info;
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/************************ End of chipdb section. ************************/
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struct BelIterator
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{
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int cursor;
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@ -485,9 +279,6 @@ struct ArchArgs
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struct Arch : BaseCtx
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{
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bool fast_part;
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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int width;
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int height;
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@ -77,7 +77,7 @@ class ChainConstrainer
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bool start_of_chain = true;
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std::vector<CellChain> chains;
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std::vector<const CellInfo *> tile;
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const int max_length = (ctx->chip_info->height - 2) * 8 - 2;
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const int max_length = (torc_info->height - 2) * 8 - 2;
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auto curr_cell = carryc.cells.begin();
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while (curr_cell != carryc.cells.end()) {
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CellInfo *cell = *curr_cell;
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1280
xc7/chipdb.py
1280
xc7/chipdb.py
File diff suppressed because it is too large
Load Diff
@ -87,8 +87,6 @@ void Xc7CommandHandler::customBitstream(Context *ctx)
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void Xc7CommandHandler::setupArchContext(Context *ctx)
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{
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// if (vm.count("tmfuzz"))
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// ice40DelayFuzzerMain(ctx);
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}
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std::unique_ptr<Context> Xc7CommandHandler::createContext()
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357
xc7/tmfuzz.py
357
xc7/tmfuzz.py
@ -1,357 +0,0 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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# ../nextpnr-ice40 --hx8k --tmfuzz > tmfuzz_hx8k.txt
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# ../nextpnr-ice40 --lp8k --tmfuzz > tmfuzz_lp8k.txt
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# ../nextpnr-ice40 --up5k --tmfuzz > tmfuzz_up5k.txt
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import numpy as np
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import matplotlib.pyplot as plt
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from collections import defaultdict
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device = "hx8k"
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# device = "lp8k"
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# device = "up5k"
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sel_src_type = "LUTFF_OUT"
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sel_dst_type = "LUTFF_IN_LUT"
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#%% Read fuzz data
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src_dst_pairs = defaultdict(lambda: 0)
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delay_data = list()
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all_delay_data = list()
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delay_map_sum = np.zeros((41, 41))
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delay_map_sum2 = np.zeros((41, 41))
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delay_map_count = np.zeros((41, 41))
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same_tile_delays = list()
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neighbour_tile_delays = list()
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type_delta_data = dict()
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with open("tmfuzz_%s.txt" % device, "r") as f:
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for line in f:
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line = line.split()
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if line[0] == "dst":
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dst_xy = (int(line[1]), int(line[2]))
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dst_type = line[3]
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dst_wire = line[4]
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src_xy = (int(line[1]), int(line[2]))
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src_type = line[3]
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src_wire = line[4]
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delay = int(line[5])
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estdelay = int(line[6])
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all_delay_data.append((delay, estdelay))
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src_dst_pairs[src_type, dst_type] += 1
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dx = dst_xy[0] - src_xy[0]
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dy = dst_xy[1] - src_xy[1]
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if src_type == sel_src_type and dst_type == sel_dst_type:
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if dx == 0 and dy == 0:
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same_tile_delays.append(delay)
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elif abs(dx) <= 1 and abs(dy) <= 1:
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neighbour_tile_delays.append(delay)
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else:
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delay_data.append((delay, estdelay, dx, dy, 0, 0, 0))
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relx = 20 + dst_xy[0] - src_xy[0]
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rely = 20 + dst_xy[1] - src_xy[1]
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if (0 <= relx <= 40) and (0 <= rely <= 40):
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delay_map_sum[relx, rely] += delay
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delay_map_sum2[relx, rely] += delay*delay
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delay_map_count[relx, rely] += 1
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if dst_type == sel_dst_type:
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if src_type not in type_delta_data:
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type_delta_data[src_type] = list()
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type_delta_data[src_type].append((dx, dy, delay))
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delay_data = np.array(delay_data)
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all_delay_data = np.array(all_delay_data)
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max_delay = np.max(delay_data[:, 0:2])
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mean_same_tile_delays = np.mean(neighbour_tile_delays)
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mean_neighbour_tile_delays = np.mean(neighbour_tile_delays)
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print("Avg same tile delay: %.2f (%.2f std, N=%d)" % \
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(mean_same_tile_delays, np.std(same_tile_delays), len(same_tile_delays)))
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print("Avg neighbour tile delay: %.2f (%.2f std, N=%d)" % \
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(mean_neighbour_tile_delays, np.std(neighbour_tile_delays), len(neighbour_tile_delays)))
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#%% Apply simple low-weight bluring to fill gaps
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for i in range(0):
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neigh_sum = np.zeros((41, 41))
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neigh_sum2 = np.zeros((41, 41))
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neigh_count = np.zeros((41, 41))
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for x in range(41):
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for y in range(41):
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for p in range(-1, 2):
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for q in range(-1, 2):
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if p == 0 and q == 0:
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continue
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if 0 <= (x+p) <= 40:
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if 0 <= (y+q) <= 40:
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neigh_sum[x, y] += delay_map_sum[x+p, y+q]
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neigh_sum2[x, y] += delay_map_sum2[x+p, y+q]
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neigh_count[x, y] += delay_map_count[x+p, y+q]
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delay_map_sum += 0.1 * neigh_sum
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delay_map_sum2 += 0.1 * neigh_sum2
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delay_map_count += 0.1 * neigh_count
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delay_map = delay_map_sum / delay_map_count
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delay_map_std = np.sqrt(delay_map_count*delay_map_sum2 - delay_map_sum**2) / delay_map_count
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#%% Print src-dst-pair summary
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print("Src-Dst-Type pair summary:")
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for cnt, src, dst in sorted([(v, k[0], k[1]) for k, v in src_dst_pairs.items()]):
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print("%20s %20s %5d%s" % (src, dst, cnt, " *" if src == sel_src_type and dst == sel_dst_type else ""))
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print()
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#%% Plot estimate vs actual delay
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plt.figure(figsize=(8, 3))
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plt.title("Estimate vs Actual Delay")
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plt.plot(all_delay_data[:, 0], all_delay_data[:, 1], ".")
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plt.plot(delay_data[:, 0], delay_data[:, 1], ".")
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plt.plot([0, max_delay], [0, max_delay], "k")
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plt.ylabel("Estimated Delay")
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plt.xlabel("Actual Delay")
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plt.grid()
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plt.show()
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#%% Plot delay heatmap and std dev heatmap
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plt.figure(figsize=(9, 3))
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plt.subplot(121)
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plt.title("Actual Delay Map")
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plt.imshow(delay_map)
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plt.colorbar()
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plt.subplot(122)
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plt.title("Standard Deviation")
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plt.imshow(delay_map_std)
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plt.colorbar()
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plt.show()
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#%% Generate Model #0
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def nonlinearPreprocessor0(dx, dy):
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dx, dy = abs(dx), abs(dy)
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values = [1.0]
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values.append(dx + dy)
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return np.array(values)
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A = np.zeros((41*41, len(nonlinearPreprocessor0(0, 0))))
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b = np.zeros(41*41)
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index = 0
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for x in range(41):
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for y in range(41):
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if delay_map_count[x, y] > 0:
|
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A[index, :] = nonlinearPreprocessor0(x-20, y-20)
|
||||
b[index] = delay_map[x, y]
|
||||
index += 1
|
||||
|
||||
model0_params, _, _, _ = np.linalg.lstsq(A, b)
|
||||
print("Model #0 parameters:", model0_params)
|
||||
|
||||
model0_map = np.zeros((41, 41))
|
||||
for x in range(41):
|
||||
for y in range(41):
|
||||
v = np.dot(model0_params, nonlinearPreprocessor0(x-20, y-20))
|
||||
model0_map[x, y] = v
|
||||
|
||||
plt.figure(figsize=(9, 3))
|
||||
plt.subplot(121)
|
||||
plt.title("Model #0 Delay Map")
|
||||
plt.imshow(model0_map)
|
||||
plt.colorbar()
|
||||
plt.subplot(122)
|
||||
plt.title("Model #0 Error Map")
|
||||
plt.imshow(model0_map - delay_map)
|
||||
plt.colorbar()
|
||||
plt.show()
|
||||
|
||||
for i in range(delay_data.shape[0]):
|
||||
dx = delay_data[i, 2]
|
||||
dy = delay_data[i, 3]
|
||||
delay_data[i, 4] = np.dot(model0_params, nonlinearPreprocessor0(dx, dy))
|
||||
|
||||
plt.figure(figsize=(8, 3))
|
||||
plt.title("Model #0 vs Actual Delay")
|
||||
plt.plot(delay_data[:, 0], delay_data[:, 4], ".")
|
||||
plt.plot(delay_map.flat, model0_map.flat, ".")
|
||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
||||
plt.ylabel("Model #0 Delay")
|
||||
plt.xlabel("Actual Delay")
|
||||
plt.grid()
|
||||
plt.show()
|
||||
|
||||
print("In-sample RMS error: %f" % np.sqrt(np.nanmean((delay_map - model0_map)**2)))
|
||||
print("Out-of-sample RMS error: %f" % np.sqrt(np.nanmean((delay_data[:, 0] - delay_data[:, 4])**2)))
|
||||
print()
|
||||
|
||||
#%% Generate Model #1
|
||||
|
||||
def nonlinearPreprocessor1(dx, dy):
|
||||
dx, dy = abs(dx), abs(dy)
|
||||
values = [1.0]
|
||||
values.append(dx + dy) # 1-norm
|
||||
values.append((dx**2 + dy**2)**(1/2)) # 2-norm
|
||||
values.append((dx**3 + dy**3)**(1/3)) # 3-norm
|
||||
return np.array(values)
|
||||
|
||||
A = np.zeros((41*41, len(nonlinearPreprocessor1(0, 0))))
|
||||
b = np.zeros(41*41)
|
||||
|
||||
index = 0
|
||||
for x in range(41):
|
||||
for y in range(41):
|
||||
if delay_map_count[x, y] > 0:
|
||||
A[index, :] = nonlinearPreprocessor1(x-20, y-20)
|
||||
b[index] = delay_map[x, y]
|
||||
index += 1
|
||||
|
||||
model1_params, _, _, _ = np.linalg.lstsq(A, b)
|
||||
print("Model #1 parameters:", model1_params)
|
||||
|
||||
model1_map = np.zeros((41, 41))
|
||||
for x in range(41):
|
||||
for y in range(41):
|
||||
v = np.dot(model1_params, nonlinearPreprocessor1(x-20, y-20))
|
||||
model1_map[x, y] = v
|
||||
|
||||
plt.figure(figsize=(9, 3))
|
||||
plt.subplot(121)
|
||||
plt.title("Model #1 Delay Map")
|
||||
plt.imshow(model1_map)
|
||||
plt.colorbar()
|
||||
plt.subplot(122)
|
||||
plt.title("Model #1 Error Map")
|
||||
plt.imshow(model1_map - delay_map)
|
||||
plt.colorbar()
|
||||
plt.show()
|
||||
|
||||
for i in range(delay_data.shape[0]):
|
||||
dx = delay_data[i, 2]
|
||||
dy = delay_data[i, 3]
|
||||
delay_data[i, 5] = np.dot(model1_params, nonlinearPreprocessor1(dx, dy))
|
||||
|
||||
plt.figure(figsize=(8, 3))
|
||||
plt.title("Model #1 vs Actual Delay")
|
||||
plt.plot(delay_data[:, 0], delay_data[:, 5], ".")
|
||||
plt.plot(delay_map.flat, model1_map.flat, ".")
|
||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
||||
plt.ylabel("Model #1 Delay")
|
||||
plt.xlabel("Actual Delay")
|
||||
plt.grid()
|
||||
plt.show()
|
||||
|
||||
print("In-sample RMS error: %f" % np.sqrt(np.nanmean((delay_map - model1_map)**2)))
|
||||
print("Out-of-sample RMS error: %f" % np.sqrt(np.nanmean((delay_data[:, 0] - delay_data[:, 5])**2)))
|
||||
print()
|
||||
|
||||
#%% Generate Model #2
|
||||
|
||||
def nonlinearPreprocessor2(v):
|
||||
return np.array([1, v, np.sqrt(v)])
|
||||
|
||||
A = np.zeros((41*41, len(nonlinearPreprocessor2(0))))
|
||||
b = np.zeros(41*41)
|
||||
|
||||
index = 0
|
||||
for x in range(41):
|
||||
for y in range(41):
|
||||
if delay_map_count[x, y] > 0:
|
||||
A[index, :] = nonlinearPreprocessor2(model1_map[x, y])
|
||||
b[index] = delay_map[x, y]
|
||||
index += 1
|
||||
|
||||
model2_params, _, _, _ = np.linalg.lstsq(A, b)
|
||||
print("Model #2 parameters:", model2_params)
|
||||
|
||||
model2_map = np.zeros((41, 41))
|
||||
for x in range(41):
|
||||
for y in range(41):
|
||||
v = np.dot(model1_params, nonlinearPreprocessor1(x-20, y-20))
|
||||
v = np.dot(model2_params, nonlinearPreprocessor2(v))
|
||||
model2_map[x, y] = v
|
||||
|
||||
plt.figure(figsize=(9, 3))
|
||||
plt.subplot(121)
|
||||
plt.title("Model #2 Delay Map")
|
||||
plt.imshow(model2_map)
|
||||
plt.colorbar()
|
||||
plt.subplot(122)
|
||||
plt.title("Model #2 Error Map")
|
||||
plt.imshow(model2_map - delay_map)
|
||||
plt.colorbar()
|
||||
plt.show()
|
||||
|
||||
for i in range(delay_data.shape[0]):
|
||||
dx = delay_data[i, 2]
|
||||
dy = delay_data[i, 3]
|
||||
delay_data[i, 6] = np.dot(model2_params, nonlinearPreprocessor2(delay_data[i, 5]))
|
||||
|
||||
plt.figure(figsize=(8, 3))
|
||||
plt.title("Model #2 vs Actual Delay")
|
||||
plt.plot(delay_data[:, 0], delay_data[:, 6], ".")
|
||||
plt.plot(delay_map.flat, model2_map.flat, ".")
|
||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
||||
plt.ylabel("Model #2 Delay")
|
||||
plt.xlabel("Actual Delay")
|
||||
plt.grid()
|
||||
plt.show()
|
||||
|
||||
print("In-sample RMS error: %f" % np.sqrt(np.nanmean((delay_map - model2_map)**2)))
|
||||
print("Out-of-sample RMS error: %f" % np.sqrt(np.nanmean((delay_data[:, 0] - delay_data[:, 6])**2)))
|
||||
print()
|
||||
|
||||
#%% Generate deltas for different source net types
|
||||
|
||||
type_deltas = dict()
|
||||
|
||||
print("Delay deltas for different src types:")
|
||||
for src_type in sorted(type_delta_data.keys()):
|
||||
deltas = list()
|
||||
|
||||
for dx, dy, delay in type_delta_data[src_type]:
|
||||
dx = abs(dx)
|
||||
dy = abs(dy)
|
||||
|
||||
if dx > 1 or dy > 1:
|
||||
est = model0_params[0] + model0_params[1] * (dx + dy)
|
||||
else:
|
||||
est = mean_neighbour_tile_delays
|
||||
deltas.append(delay - est)
|
||||
|
||||
print("%15s: %8.2f (std %6.2f)" % (\
|
||||
src_type, np.mean(deltas), np.std(deltas)))
|
||||
|
||||
type_deltas[src_type] = np.mean(deltas)
|
||||
|
||||
#%% Print C defs of model parameters
|
||||
|
||||
print("--snip--")
|
||||
print("%d, %d, %d," % (mean_neighbour_tile_delays, 128 * model0_params[0], 128 * model0_params[1]))
|
||||
print("%d, %d, %d, %d," % (128 * model1_params[0], 128 * model1_params[1], 128 * model1_params[2], 128 * model1_params[3]))
|
||||
print("%d, %d, %d," % (128 * model2_params[0], 128 * model2_params[1], 128 * model2_params[2]))
|
||||
print("%d, %d, %d, %d" % (type_deltas["LOCAL"], type_deltas["LUTFF_IN"], \
|
||||
(type_deltas["SP4_H"] + type_deltas["SP4_V"]) / 2,
|
||||
(type_deltas["SP12_H"] + type_deltas["SP12_V"]) / 2))
|
||||
print("--snap--")
|
||||
Loading…
Reference in New Issue
Block a user