Merge pull request #201 from eddiehung/xc7
Remove some more ice40 stuff
This commit is contained in:
commit
c51d89f2af
34
xc7/arch.cc
34
xc7/arch.cc
@ -442,44 +442,14 @@ BelId Arch::getBelByLocation(Loc loc) const
|
|||||||
BelRange Arch::getBelsByTile(int x, int y) const
|
BelRange Arch::getBelsByTile(int x, int y) const
|
||||||
{
|
{
|
||||||
BelRange br;
|
BelRange br;
|
||||||
|
NPNR_ASSERT("TODO");
|
||||||
br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
|
|
||||||
br.e.cursor = br.b.cursor;
|
|
||||||
|
|
||||||
if (br.e.cursor != -1) {
|
|
||||||
while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
|
|
||||||
chip_info->bel_data[br.e.cursor].y == y)
|
|
||||||
br.e.cursor++;
|
|
||||||
}
|
|
||||||
|
|
||||||
return br;
|
return br;
|
||||||
}
|
}
|
||||||
|
|
||||||
PortType Arch::getBelPinType(BelId bel, IdString pin) const
|
PortType Arch::getBelPinType(BelId bel, IdString pin) const
|
||||||
{
|
{
|
||||||
NPNR_ASSERT(bel != BelId());
|
NPNR_ASSERT(bel != BelId());
|
||||||
|
NPNR_ASSERT("TODO");
|
||||||
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
|
|
||||||
const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
|
|
||||||
|
|
||||||
if (num_bel_wires < 7) {
|
|
||||||
for (int i = 0; i < num_bel_wires; i++) {
|
|
||||||
if (bel_wires[i].port == pin.index)
|
|
||||||
return PortType(bel_wires[i].type);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
int b = 0, e = num_bel_wires - 1;
|
|
||||||
while (b <= e) {
|
|
||||||
int i = (b + e) / 2;
|
|
||||||
if (bel_wires[i].port == pin.index)
|
|
||||||
return PortType(bel_wires[i].type);
|
|
||||||
if (bel_wires[i].port > pin.index)
|
|
||||||
e = i - 1;
|
|
||||||
else
|
|
||||||
b = i + 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return PORT_INOUT;
|
return PORT_INOUT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
209
xc7/arch.h
209
xc7/arch.h
@ -64,210 +64,6 @@ template <> struct hash<Arc>
|
|||||||
|
|
||||||
NEXTPNR_NAMESPACE_BEGIN
|
NEXTPNR_NAMESPACE_BEGIN
|
||||||
|
|
||||||
/**** Everything in this section must be kept in sync with chipdb.py ****/
|
|
||||||
|
|
||||||
template <typename T> struct RelPtr
|
|
||||||
{
|
|
||||||
int32_t offset;
|
|
||||||
|
|
||||||
// void set(const T *ptr) {
|
|
||||||
// offset = reinterpret_cast<const char*>(ptr) -
|
|
||||||
// reinterpret_cast<const char*>(this);
|
|
||||||
// }
|
|
||||||
|
|
||||||
const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
|
|
||||||
|
|
||||||
const T &operator[](size_t index) const { return get()[index]; }
|
|
||||||
|
|
||||||
const T &operator*() const { return *(get()); }
|
|
||||||
|
|
||||||
const T *operator->() const { return get(); }
|
|
||||||
};
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct BelWirePOD {
|
|
||||||
int32_t port;
|
|
||||||
int32_t type;
|
|
||||||
int32_t wire_index;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct BelInfoPOD {
|
|
||||||
RelPtr<char> name;
|
|
||||||
int32_t type;
|
|
||||||
int32_t num_bel_wires;
|
|
||||||
RelPtr<BelWirePOD> bel_wires;
|
|
||||||
int8_t x, y, z;
|
|
||||||
int8_t padding_0;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct BelPortPOD {
|
|
||||||
int32_t bel_index;
|
|
||||||
int32_t port;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct PipInfoPOD {
|
|
||||||
enum PipFlags : uint32_t
|
|
||||||
{
|
|
||||||
FLAG_NONE = 0,
|
|
||||||
FLAG_ROUTETHRU = 1,
|
|
||||||
FLAG_NOCARRY = 2
|
|
||||||
};
|
|
||||||
|
|
||||||
// RelPtr<char> name;
|
|
||||||
int32_t src, dst;
|
|
||||||
int32_t fast_delay;
|
|
||||||
int32_t slow_delay;
|
|
||||||
int8_t x, y;
|
|
||||||
int16_t src_seg, dst_seg;
|
|
||||||
int16_t switch_mask;
|
|
||||||
int32_t switch_index;
|
|
||||||
PipFlags flags;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct WireSegmentPOD {
|
|
||||||
int8_t x, y;
|
|
||||||
int16_t index;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct WireInfoPOD {
|
|
||||||
enum WireType : int8_t
|
|
||||||
{
|
|
||||||
WIRE_TYPE_NONE = 0,
|
|
||||||
WIRE_TYPE_GLB2LOCAL = 1,
|
|
||||||
WIRE_TYPE_GLB_NETWK = 2,
|
|
||||||
WIRE_TYPE_LOCAL = 3,
|
|
||||||
WIRE_TYPE_LUTFF_IN = 4,
|
|
||||||
WIRE_TYPE_LUTFF_IN_LUT = 5,
|
|
||||||
WIRE_TYPE_LUTFF_LOUT = 6,
|
|
||||||
WIRE_TYPE_LUTFF_OUT = 7,
|
|
||||||
WIRE_TYPE_LUTFF_COUT = 8,
|
|
||||||
WIRE_TYPE_LUTFF_GLOBAL = 9,
|
|
||||||
WIRE_TYPE_CARRY_IN_MUX = 10,
|
|
||||||
WIRE_TYPE_SP4_V = 11,
|
|
||||||
WIRE_TYPE_SP4_H = 12,
|
|
||||||
WIRE_TYPE_SP12_V = 13,
|
|
||||||
WIRE_TYPE_SP12_H = 14
|
|
||||||
};
|
|
||||||
|
|
||||||
RelPtr<char> name;
|
|
||||||
int32_t num_uphill, num_downhill;
|
|
||||||
RelPtr<int32_t> pips_uphill, pips_downhill;
|
|
||||||
|
|
||||||
int32_t num_bel_pins;
|
|
||||||
RelPtr<BelPortPOD> bel_pins;
|
|
||||||
|
|
||||||
int32_t num_segments;
|
|
||||||
RelPtr<WireSegmentPOD> segments;
|
|
||||||
|
|
||||||
int32_t fast_delay;
|
|
||||||
int32_t slow_delay;
|
|
||||||
|
|
||||||
int8_t x, y, z;
|
|
||||||
WireType type;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct PackagePinPOD {
|
|
||||||
RelPtr<char> name;
|
|
||||||
int32_t bel_index;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct PackageInfoPOD {
|
|
||||||
RelPtr<char> name;
|
|
||||||
int32_t num_pins;
|
|
||||||
RelPtr<PackagePinPOD> pins;
|
|
||||||
});
|
|
||||||
|
|
||||||
enum TileType : uint32_t
|
|
||||||
{
|
|
||||||
TILE_NONE = 0,
|
|
||||||
TILE_LOGIC = 1,
|
|
||||||
TILE_IO = 2,
|
|
||||||
TILE_RAMB = 3,
|
|
||||||
TILE_RAMT = 4,
|
|
||||||
TILE_DSP0 = 5,
|
|
||||||
TILE_DSP1 = 6,
|
|
||||||
TILE_DSP2 = 7,
|
|
||||||
TILE_DSP3 = 8,
|
|
||||||
TILE_IPCON = 9
|
|
||||||
};
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct ConfigBitPOD { int8_t row, col; });
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct ConfigEntryPOD {
|
|
||||||
RelPtr<char> name;
|
|
||||||
int32_t num_bits;
|
|
||||||
RelPtr<ConfigBitPOD> bits;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct TileInfoPOD {
|
|
||||||
int8_t cols, rows;
|
|
||||||
int16_t num_config_entries;
|
|
||||||
RelPtr<ConfigEntryPOD> entries;
|
|
||||||
});
|
|
||||||
|
|
||||||
static const int max_switch_bits = 5;
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct SwitchInfoPOD {
|
|
||||||
int32_t num_bits;
|
|
||||||
int32_t bel;
|
|
||||||
int8_t x, y;
|
|
||||||
ConfigBitPOD cbits[max_switch_bits];
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct IerenInfoPOD {
|
|
||||||
int8_t iox, ioy, ioz;
|
|
||||||
int8_t ierx, iery, ierz;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct BitstreamInfoPOD {
|
|
||||||
int32_t num_switches, num_ierens;
|
|
||||||
RelPtr<TileInfoPOD> tiles_nonrouting;
|
|
||||||
RelPtr<SwitchInfoPOD> switches;
|
|
||||||
RelPtr<IerenInfoPOD> ierens;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct BelConfigEntryPOD {
|
|
||||||
RelPtr<char> entry_name;
|
|
||||||
RelPtr<char> cbit_name;
|
|
||||||
int8_t x, y;
|
|
||||||
int16_t padding;
|
|
||||||
});
|
|
||||||
|
|
||||||
// Stores mapping between bel parameters and config bits,
|
|
||||||
// for extra cells where this mapping is non-trivial
|
|
||||||
NPNR_PACKED_STRUCT(struct BelConfigPOD {
|
|
||||||
int32_t bel_index;
|
|
||||||
int32_t num_entries;
|
|
||||||
RelPtr<BelConfigEntryPOD> entries;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct CellPathDelayPOD {
|
|
||||||
int32_t from_port;
|
|
||||||
int32_t to_port;
|
|
||||||
int32_t fast_delay;
|
|
||||||
int32_t slow_delay;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct CellTimingPOD {
|
|
||||||
int32_t type;
|
|
||||||
int32_t num_paths;
|
|
||||||
RelPtr<CellPathDelayPOD> path_delays;
|
|
||||||
});
|
|
||||||
|
|
||||||
NPNR_PACKED_STRUCT(struct ChipInfoPOD {
|
|
||||||
int32_t width, height;
|
|
||||||
int32_t num_bels, num_wires, num_pips;
|
|
||||||
int32_t num_switches, num_belcfgs, num_packages;
|
|
||||||
int32_t num_timing_cells;
|
|
||||||
RelPtr<BelInfoPOD> bel_data;
|
|
||||||
RelPtr<WireInfoPOD> wire_data;
|
|
||||||
RelPtr<PipInfoPOD> pip_data;
|
|
||||||
RelPtr<TileType> tile_grid;
|
|
||||||
RelPtr<BitstreamInfoPOD> bits_info;
|
|
||||||
RelPtr<BelConfigPOD> bel_config;
|
|
||||||
RelPtr<PackageInfoPOD> packages_data;
|
|
||||||
RelPtr<CellTimingPOD> cell_timing;
|
|
||||||
});
|
|
||||||
|
|
||||||
struct TorcInfo
|
struct TorcInfo
|
||||||
{
|
{
|
||||||
TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName);
|
TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName);
|
||||||
@ -339,8 +135,6 @@ struct TorcInfo
|
|||||||
};
|
};
|
||||||
extern std::unique_ptr<const TorcInfo> torc_info;
|
extern std::unique_ptr<const TorcInfo> torc_info;
|
||||||
|
|
||||||
/************************ End of chipdb section. ************************/
|
|
||||||
|
|
||||||
struct BelIterator
|
struct BelIterator
|
||||||
{
|
{
|
||||||
int cursor;
|
int cursor;
|
||||||
@ -485,9 +279,6 @@ struct ArchArgs
|
|||||||
|
|
||||||
struct Arch : BaseCtx
|
struct Arch : BaseCtx
|
||||||
{
|
{
|
||||||
bool fast_part;
|
|
||||||
const ChipInfoPOD *chip_info;
|
|
||||||
const PackageInfoPOD *package_info;
|
|
||||||
int width;
|
int width;
|
||||||
int height;
|
int height;
|
||||||
|
|
||||||
|
@ -77,7 +77,7 @@ class ChainConstrainer
|
|||||||
bool start_of_chain = true;
|
bool start_of_chain = true;
|
||||||
std::vector<CellChain> chains;
|
std::vector<CellChain> chains;
|
||||||
std::vector<const CellInfo *> tile;
|
std::vector<const CellInfo *> tile;
|
||||||
const int max_length = (ctx->chip_info->height - 2) * 8 - 2;
|
const int max_length = (torc_info->height - 2) * 8 - 2;
|
||||||
auto curr_cell = carryc.cells.begin();
|
auto curr_cell = carryc.cells.begin();
|
||||||
while (curr_cell != carryc.cells.end()) {
|
while (curr_cell != carryc.cells.end()) {
|
||||||
CellInfo *cell = *curr_cell;
|
CellInfo *cell = *curr_cell;
|
||||||
|
1280
xc7/chipdb.py
1280
xc7/chipdb.py
File diff suppressed because it is too large
Load Diff
@ -87,8 +87,6 @@ void Xc7CommandHandler::customBitstream(Context *ctx)
|
|||||||
|
|
||||||
void Xc7CommandHandler::setupArchContext(Context *ctx)
|
void Xc7CommandHandler::setupArchContext(Context *ctx)
|
||||||
{
|
{
|
||||||
// if (vm.count("tmfuzz"))
|
|
||||||
// ice40DelayFuzzerMain(ctx);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
std::unique_ptr<Context> Xc7CommandHandler::createContext()
|
std::unique_ptr<Context> Xc7CommandHandler::createContext()
|
||||||
|
357
xc7/tmfuzz.py
357
xc7/tmfuzz.py
@ -1,357 +0,0 @@
|
|||||||
#!/usr/bin/env python3
|
|
||||||
# -*- coding: utf-8 -*-
|
|
||||||
# ../nextpnr-ice40 --hx8k --tmfuzz > tmfuzz_hx8k.txt
|
|
||||||
# ../nextpnr-ice40 --lp8k --tmfuzz > tmfuzz_lp8k.txt
|
|
||||||
# ../nextpnr-ice40 --up5k --tmfuzz > tmfuzz_up5k.txt
|
|
||||||
|
|
||||||
import numpy as np
|
|
||||||
import matplotlib.pyplot as plt
|
|
||||||
from collections import defaultdict
|
|
||||||
|
|
||||||
device = "hx8k"
|
|
||||||
# device = "lp8k"
|
|
||||||
# device = "up5k"
|
|
||||||
|
|
||||||
sel_src_type = "LUTFF_OUT"
|
|
||||||
sel_dst_type = "LUTFF_IN_LUT"
|
|
||||||
|
|
||||||
#%% Read fuzz data
|
|
||||||
|
|
||||||
src_dst_pairs = defaultdict(lambda: 0)
|
|
||||||
|
|
||||||
delay_data = list()
|
|
||||||
all_delay_data = list()
|
|
||||||
|
|
||||||
delay_map_sum = np.zeros((41, 41))
|
|
||||||
delay_map_sum2 = np.zeros((41, 41))
|
|
||||||
delay_map_count = np.zeros((41, 41))
|
|
||||||
|
|
||||||
same_tile_delays = list()
|
|
||||||
neighbour_tile_delays = list()
|
|
||||||
|
|
||||||
type_delta_data = dict()
|
|
||||||
|
|
||||||
with open("tmfuzz_%s.txt" % device, "r") as f:
|
|
||||||
for line in f:
|
|
||||||
line = line.split()
|
|
||||||
|
|
||||||
if line[0] == "dst":
|
|
||||||
dst_xy = (int(line[1]), int(line[2]))
|
|
||||||
dst_type = line[3]
|
|
||||||
dst_wire = line[4]
|
|
||||||
|
|
||||||
src_xy = (int(line[1]), int(line[2]))
|
|
||||||
src_type = line[3]
|
|
||||||
src_wire = line[4]
|
|
||||||
|
|
||||||
delay = int(line[5])
|
|
||||||
estdelay = int(line[6])
|
|
||||||
|
|
||||||
all_delay_data.append((delay, estdelay))
|
|
||||||
|
|
||||||
src_dst_pairs[src_type, dst_type] += 1
|
|
||||||
|
|
||||||
dx = dst_xy[0] - src_xy[0]
|
|
||||||
dy = dst_xy[1] - src_xy[1]
|
|
||||||
|
|
||||||
if src_type == sel_src_type and dst_type == sel_dst_type:
|
|
||||||
if dx == 0 and dy == 0:
|
|
||||||
same_tile_delays.append(delay)
|
|
||||||
|
|
||||||
elif abs(dx) <= 1 and abs(dy) <= 1:
|
|
||||||
neighbour_tile_delays.append(delay)
|
|
||||||
|
|
||||||
else:
|
|
||||||
delay_data.append((delay, estdelay, dx, dy, 0, 0, 0))
|
|
||||||
|
|
||||||
relx = 20 + dst_xy[0] - src_xy[0]
|
|
||||||
rely = 20 + dst_xy[1] - src_xy[1]
|
|
||||||
|
|
||||||
if (0 <= relx <= 40) and (0 <= rely <= 40):
|
|
||||||
delay_map_sum[relx, rely] += delay
|
|
||||||
delay_map_sum2[relx, rely] += delay*delay
|
|
||||||
delay_map_count[relx, rely] += 1
|
|
||||||
|
|
||||||
if dst_type == sel_dst_type:
|
|
||||||
if src_type not in type_delta_data:
|
|
||||||
type_delta_data[src_type] = list()
|
|
||||||
|
|
||||||
type_delta_data[src_type].append((dx, dy, delay))
|
|
||||||
|
|
||||||
delay_data = np.array(delay_data)
|
|
||||||
all_delay_data = np.array(all_delay_data)
|
|
||||||
max_delay = np.max(delay_data[:, 0:2])
|
|
||||||
|
|
||||||
mean_same_tile_delays = np.mean(neighbour_tile_delays)
|
|
||||||
mean_neighbour_tile_delays = np.mean(neighbour_tile_delays)
|
|
||||||
|
|
||||||
print("Avg same tile delay: %.2f (%.2f std, N=%d)" % \
|
|
||||||
(mean_same_tile_delays, np.std(same_tile_delays), len(same_tile_delays)))
|
|
||||||
print("Avg neighbour tile delay: %.2f (%.2f std, N=%d)" % \
|
|
||||||
(mean_neighbour_tile_delays, np.std(neighbour_tile_delays), len(neighbour_tile_delays)))
|
|
||||||
|
|
||||||
#%% Apply simple low-weight bluring to fill gaps
|
|
||||||
|
|
||||||
for i in range(0):
|
|
||||||
neigh_sum = np.zeros((41, 41))
|
|
||||||
neigh_sum2 = np.zeros((41, 41))
|
|
||||||
neigh_count = np.zeros((41, 41))
|
|
||||||
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
for p in range(-1, 2):
|
|
||||||
for q in range(-1, 2):
|
|
||||||
if p == 0 and q == 0:
|
|
||||||
continue
|
|
||||||
if 0 <= (x+p) <= 40:
|
|
||||||
if 0 <= (y+q) <= 40:
|
|
||||||
neigh_sum[x, y] += delay_map_sum[x+p, y+q]
|
|
||||||
neigh_sum2[x, y] += delay_map_sum2[x+p, y+q]
|
|
||||||
neigh_count[x, y] += delay_map_count[x+p, y+q]
|
|
||||||
|
|
||||||
delay_map_sum += 0.1 * neigh_sum
|
|
||||||
delay_map_sum2 += 0.1 * neigh_sum2
|
|
||||||
delay_map_count += 0.1 * neigh_count
|
|
||||||
|
|
||||||
delay_map = delay_map_sum / delay_map_count
|
|
||||||
delay_map_std = np.sqrt(delay_map_count*delay_map_sum2 - delay_map_sum**2) / delay_map_count
|
|
||||||
|
|
||||||
#%% Print src-dst-pair summary
|
|
||||||
|
|
||||||
print("Src-Dst-Type pair summary:")
|
|
||||||
for cnt, src, dst in sorted([(v, k[0], k[1]) for k, v in src_dst_pairs.items()]):
|
|
||||||
print("%20s %20s %5d%s" % (src, dst, cnt, " *" if src == sel_src_type and dst == sel_dst_type else ""))
|
|
||||||
print()
|
|
||||||
|
|
||||||
#%% Plot estimate vs actual delay
|
|
||||||
|
|
||||||
plt.figure(figsize=(8, 3))
|
|
||||||
plt.title("Estimate vs Actual Delay")
|
|
||||||
plt.plot(all_delay_data[:, 0], all_delay_data[:, 1], ".")
|
|
||||||
plt.plot(delay_data[:, 0], delay_data[:, 1], ".")
|
|
||||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
|
||||||
plt.ylabel("Estimated Delay")
|
|
||||||
plt.xlabel("Actual Delay")
|
|
||||||
plt.grid()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
#%% Plot delay heatmap and std dev heatmap
|
|
||||||
|
|
||||||
plt.figure(figsize=(9, 3))
|
|
||||||
plt.subplot(121)
|
|
||||||
plt.title("Actual Delay Map")
|
|
||||||
plt.imshow(delay_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.subplot(122)
|
|
||||||
plt.title("Standard Deviation")
|
|
||||||
plt.imshow(delay_map_std)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
#%% Generate Model #0
|
|
||||||
|
|
||||||
def nonlinearPreprocessor0(dx, dy):
|
|
||||||
dx, dy = abs(dx), abs(dy)
|
|
||||||
values = [1.0]
|
|
||||||
values.append(dx + dy)
|
|
||||||
return np.array(values)
|
|
||||||
|
|
||||||
A = np.zeros((41*41, len(nonlinearPreprocessor0(0, 0))))
|
|
||||||
b = np.zeros(41*41)
|
|
||||||
|
|
||||||
index = 0
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
if delay_map_count[x, y] > 0:
|
|
||||||
A[index, :] = nonlinearPreprocessor0(x-20, y-20)
|
|
||||||
b[index] = delay_map[x, y]
|
|
||||||
index += 1
|
|
||||||
|
|
||||||
model0_params, _, _, _ = np.linalg.lstsq(A, b)
|
|
||||||
print("Model #0 parameters:", model0_params)
|
|
||||||
|
|
||||||
model0_map = np.zeros((41, 41))
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
v = np.dot(model0_params, nonlinearPreprocessor0(x-20, y-20))
|
|
||||||
model0_map[x, y] = v
|
|
||||||
|
|
||||||
plt.figure(figsize=(9, 3))
|
|
||||||
plt.subplot(121)
|
|
||||||
plt.title("Model #0 Delay Map")
|
|
||||||
plt.imshow(model0_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.subplot(122)
|
|
||||||
plt.title("Model #0 Error Map")
|
|
||||||
plt.imshow(model0_map - delay_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
for i in range(delay_data.shape[0]):
|
|
||||||
dx = delay_data[i, 2]
|
|
||||||
dy = delay_data[i, 3]
|
|
||||||
delay_data[i, 4] = np.dot(model0_params, nonlinearPreprocessor0(dx, dy))
|
|
||||||
|
|
||||||
plt.figure(figsize=(8, 3))
|
|
||||||
plt.title("Model #0 vs Actual Delay")
|
|
||||||
plt.plot(delay_data[:, 0], delay_data[:, 4], ".")
|
|
||||||
plt.plot(delay_map.flat, model0_map.flat, ".")
|
|
||||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
|
||||||
plt.ylabel("Model #0 Delay")
|
|
||||||
plt.xlabel("Actual Delay")
|
|
||||||
plt.grid()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
print("In-sample RMS error: %f" % np.sqrt(np.nanmean((delay_map - model0_map)**2)))
|
|
||||||
print("Out-of-sample RMS error: %f" % np.sqrt(np.nanmean((delay_data[:, 0] - delay_data[:, 4])**2)))
|
|
||||||
print()
|
|
||||||
|
|
||||||
#%% Generate Model #1
|
|
||||||
|
|
||||||
def nonlinearPreprocessor1(dx, dy):
|
|
||||||
dx, dy = abs(dx), abs(dy)
|
|
||||||
values = [1.0]
|
|
||||||
values.append(dx + dy) # 1-norm
|
|
||||||
values.append((dx**2 + dy**2)**(1/2)) # 2-norm
|
|
||||||
values.append((dx**3 + dy**3)**(1/3)) # 3-norm
|
|
||||||
return np.array(values)
|
|
||||||
|
|
||||||
A = np.zeros((41*41, len(nonlinearPreprocessor1(0, 0))))
|
|
||||||
b = np.zeros(41*41)
|
|
||||||
|
|
||||||
index = 0
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
if delay_map_count[x, y] > 0:
|
|
||||||
A[index, :] = nonlinearPreprocessor1(x-20, y-20)
|
|
||||||
b[index] = delay_map[x, y]
|
|
||||||
index += 1
|
|
||||||
|
|
||||||
model1_params, _, _, _ = np.linalg.lstsq(A, b)
|
|
||||||
print("Model #1 parameters:", model1_params)
|
|
||||||
|
|
||||||
model1_map = np.zeros((41, 41))
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
v = np.dot(model1_params, nonlinearPreprocessor1(x-20, y-20))
|
|
||||||
model1_map[x, y] = v
|
|
||||||
|
|
||||||
plt.figure(figsize=(9, 3))
|
|
||||||
plt.subplot(121)
|
|
||||||
plt.title("Model #1 Delay Map")
|
|
||||||
plt.imshow(model1_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.subplot(122)
|
|
||||||
plt.title("Model #1 Error Map")
|
|
||||||
plt.imshow(model1_map - delay_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
for i in range(delay_data.shape[0]):
|
|
||||||
dx = delay_data[i, 2]
|
|
||||||
dy = delay_data[i, 3]
|
|
||||||
delay_data[i, 5] = np.dot(model1_params, nonlinearPreprocessor1(dx, dy))
|
|
||||||
|
|
||||||
plt.figure(figsize=(8, 3))
|
|
||||||
plt.title("Model #1 vs Actual Delay")
|
|
||||||
plt.plot(delay_data[:, 0], delay_data[:, 5], ".")
|
|
||||||
plt.plot(delay_map.flat, model1_map.flat, ".")
|
|
||||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
|
||||||
plt.ylabel("Model #1 Delay")
|
|
||||||
plt.xlabel("Actual Delay")
|
|
||||||
plt.grid()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
print("In-sample RMS error: %f" % np.sqrt(np.nanmean((delay_map - model1_map)**2)))
|
|
||||||
print("Out-of-sample RMS error: %f" % np.sqrt(np.nanmean((delay_data[:, 0] - delay_data[:, 5])**2)))
|
|
||||||
print()
|
|
||||||
|
|
||||||
#%% Generate Model #2
|
|
||||||
|
|
||||||
def nonlinearPreprocessor2(v):
|
|
||||||
return np.array([1, v, np.sqrt(v)])
|
|
||||||
|
|
||||||
A = np.zeros((41*41, len(nonlinearPreprocessor2(0))))
|
|
||||||
b = np.zeros(41*41)
|
|
||||||
|
|
||||||
index = 0
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
if delay_map_count[x, y] > 0:
|
|
||||||
A[index, :] = nonlinearPreprocessor2(model1_map[x, y])
|
|
||||||
b[index] = delay_map[x, y]
|
|
||||||
index += 1
|
|
||||||
|
|
||||||
model2_params, _, _, _ = np.linalg.lstsq(A, b)
|
|
||||||
print("Model #2 parameters:", model2_params)
|
|
||||||
|
|
||||||
model2_map = np.zeros((41, 41))
|
|
||||||
for x in range(41):
|
|
||||||
for y in range(41):
|
|
||||||
v = np.dot(model1_params, nonlinearPreprocessor1(x-20, y-20))
|
|
||||||
v = np.dot(model2_params, nonlinearPreprocessor2(v))
|
|
||||||
model2_map[x, y] = v
|
|
||||||
|
|
||||||
plt.figure(figsize=(9, 3))
|
|
||||||
plt.subplot(121)
|
|
||||||
plt.title("Model #2 Delay Map")
|
|
||||||
plt.imshow(model2_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.subplot(122)
|
|
||||||
plt.title("Model #2 Error Map")
|
|
||||||
plt.imshow(model2_map - delay_map)
|
|
||||||
plt.colorbar()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
for i in range(delay_data.shape[0]):
|
|
||||||
dx = delay_data[i, 2]
|
|
||||||
dy = delay_data[i, 3]
|
|
||||||
delay_data[i, 6] = np.dot(model2_params, nonlinearPreprocessor2(delay_data[i, 5]))
|
|
||||||
|
|
||||||
plt.figure(figsize=(8, 3))
|
|
||||||
plt.title("Model #2 vs Actual Delay")
|
|
||||||
plt.plot(delay_data[:, 0], delay_data[:, 6], ".")
|
|
||||||
plt.plot(delay_map.flat, model2_map.flat, ".")
|
|
||||||
plt.plot([0, max_delay], [0, max_delay], "k")
|
|
||||||
plt.ylabel("Model #2 Delay")
|
|
||||||
plt.xlabel("Actual Delay")
|
|
||||||
plt.grid()
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
print("In-sample RMS error: %f" % np.sqrt(np.nanmean((delay_map - model2_map)**2)))
|
|
||||||
print("Out-of-sample RMS error: %f" % np.sqrt(np.nanmean((delay_data[:, 0] - delay_data[:, 6])**2)))
|
|
||||||
print()
|
|
||||||
|
|
||||||
#%% Generate deltas for different source net types
|
|
||||||
|
|
||||||
type_deltas = dict()
|
|
||||||
|
|
||||||
print("Delay deltas for different src types:")
|
|
||||||
for src_type in sorted(type_delta_data.keys()):
|
|
||||||
deltas = list()
|
|
||||||
|
|
||||||
for dx, dy, delay in type_delta_data[src_type]:
|
|
||||||
dx = abs(dx)
|
|
||||||
dy = abs(dy)
|
|
||||||
|
|
||||||
if dx > 1 or dy > 1:
|
|
||||||
est = model0_params[0] + model0_params[1] * (dx + dy)
|
|
||||||
else:
|
|
||||||
est = mean_neighbour_tile_delays
|
|
||||||
deltas.append(delay - est)
|
|
||||||
|
|
||||||
print("%15s: %8.2f (std %6.2f)" % (\
|
|
||||||
src_type, np.mean(deltas), np.std(deltas)))
|
|
||||||
|
|
||||||
type_deltas[src_type] = np.mean(deltas)
|
|
||||||
|
|
||||||
#%% Print C defs of model parameters
|
|
||||||
|
|
||||||
print("--snip--")
|
|
||||||
print("%d, %d, %d," % (mean_neighbour_tile_delays, 128 * model0_params[0], 128 * model0_params[1]))
|
|
||||||
print("%d, %d, %d, %d," % (128 * model1_params[0], 128 * model1_params[1], 128 * model1_params[2], 128 * model1_params[3]))
|
|
||||||
print("%d, %d, %d," % (128 * model2_params[0], 128 * model2_params[1], 128 * model2_params[2]))
|
|
||||||
print("%d, %d, %d, %d" % (type_deltas["LOCAL"], type_deltas["LUTFF_IN"], \
|
|
||||||
(type_deltas["SP4_H"] + type_deltas["SP4_V"]) / 2,
|
|
||||||
(type_deltas["SP12_H"] + type_deltas["SP12_V"]) / 2))
|
|
||||||
print("--snap--")
|
|
Loading…
Reference in New Issue
Block a user