gowin: Rename questionable ports
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
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38eb1f05ff
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c52906e8bc
@ -420,7 +420,7 @@ void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
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{
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{
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NPNR_ASSERT(bels.count(name) == 0);
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NPNR_ASSERT(bels.count(name) == 0);
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NPNR_ASSERT(bel_by_loc.count(loc) == 0);
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NPNR_ASSERT(bel_by_loc.count(loc) == 0);
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BelInfo &bi = bels[name];
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BelInfo &bi = bels.at(name);
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bi.name = name;
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bi.name = name;
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bi.type = type;
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bi.type = type;
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bi.x = loc.x;
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bi.x = loc.x;
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@ -1572,23 +1572,23 @@ Arch::Arch(ArchArgs args) : args(args)
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_OEN, id(buf));
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addBelInput(belname, id_OEN, id(buf));
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// GW1NR-9 quirk
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// GW1NR-9 quirk
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const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS0);
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const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_GW9_ALWAYS_LOW0);
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if (xxx_port != nullptr) {
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if (quirk_port != nullptr) {
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gw1n9_quirk = true;
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gw1n9_quirk = true;
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portname = IdString(xxx_port->src_id);
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portname = IdString(quirk_port->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_XXX_VSS0, id(buf));
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addBelInput(belname, id_GW9_ALWAYS_LOW0, id(buf));
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}
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}
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xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS1);
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quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_GW9_ALWAYS_LOW1);
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if (xxx_port != nullptr) {
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if (quirk_port != nullptr) {
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gw1n9_quirk = true;
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gw1n9_quirk = true;
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portname = IdString(xxx_port->src_id);
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portname = IdString(quirk_port->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_XXX_VSS1, id(buf));
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addBelInput(belname, id_GW9_ALWAYS_LOW1, id(buf));
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}
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}
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if (!z && device_id == id("GW1NR-9C")) {
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if (!z && device_id == id("GW1NR-9C")) {
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addBelInput(belname, id_XXX_0, idf("R%dC%d_C6", row + 1, col + 1));
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addBelInput(belname, id_GW9C_ALWAYS_LOW0, idf("R%dC%d_C6", row + 1, col + 1));
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addBelInput(belname, id_XXX_1, idf("R%dC%d_D6", row + 1, col + 1));
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addBelInput(belname, id_GW9C_ALWAYS_LOW1, idf("R%dC%d_D6", row + 1, col + 1));
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}
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}
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} break;
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} break;
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// Simplified IO
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// Simplified IO
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@ -1654,19 +1654,19 @@ Arch::Arch(ArchArgs args) : args(args)
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_CLK, id(buf));
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addBelInput(belname, id_CLK, id(buf));
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const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS);
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const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_LOW);
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if (xxx_port != nullptr) {
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if (quirk_port != nullptr) {
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ddr_has_extra_inputs = true;
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ddr_has_extra_inputs = true;
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portname = IdString(xxx_port->src_id);
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portname = IdString(quirk_port->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_XXX_VSS, id(buf));
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addBelInput(belname, id_ODDR_ALWAYS_LOW, id(buf));
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}
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}
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xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VCC);
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quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_HIGH);
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if (xxx_port != nullptr) {
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if (quirk_port != nullptr) {
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ddr_has_extra_inputs = true;
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ddr_has_extra_inputs = true;
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portname = IdString(xxx_port->src_id);
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portname = IdString(quirk_port->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_XXX_VCC, id(buf));
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addBelInput(belname, id_ODDR_ALWAYS_HIGH, id(buf));
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}
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}
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if (oddrc) {
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if (oddrc) {
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@ -2344,7 +2344,7 @@ void Arch::mark_used_hclk(Context *ctx)
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log_info(" Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(this), user.port.c_str(this),
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log_info(" Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(this), user.port.c_str(this),
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dstWire.c_str(this));
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dstWire.c_str(this));
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}
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}
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for (PipId const &pip : getPipsUphill(dstWire)) {
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for (PipId pip : getPipsUphill(dstWire)) {
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if (!checkPipAvail(pip)) {
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if (!checkPipAvail(pip)) {
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WireId src_wire = getPipSrcWire(pip);
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WireId src_wire = getPipSrcWire(pip);
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ci->setAttr(id_IOLOGIC_FCLK, Property(wire_info(src_wire).type.str(this)));
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ci->setAttr(id_IOLOGIC_FCLK, Property(wire_info(src_wire).type.str(this)));
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@ -766,12 +766,12 @@ X(TX2)
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X(TX3)
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X(TX3)
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X(FCLK)
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X(FCLK)
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X(PCLK)
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X(PCLK)
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X(XXX_VSS)
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X(ODDR_ALWAYS_LOW)
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X(XXX_VCC)
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X(ODDR_ALWAYS_HIGH)
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X(XXX_VSS0)
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X(GW9_ALWAYS_LOW0)
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X(XXX_VSS1)
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X(GW9_ALWAYS_LOW1)
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X(XXX_0)
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X(GW9C_ALWAYS_LOW0)
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X(XXX_1)
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X(GW9C_ALWAYS_LOW1)
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X(OBUF_TYPE)
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X(OBUF_TYPE)
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X(SBUF)
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X(SBUF)
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X(DBUF)
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X(DBUF)
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@ -890,20 +890,20 @@ static void pack_iologic(Context *ctx)
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}
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}
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// if have XXX_ inputs connect them
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// if have XXX_ inputs connect them
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if (ctx->ddr_has_extra_inputs) {
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if (ctx->ddr_has_extra_inputs) {
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ci->addInput(id_XXX_VSS);
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ci->addInput(id_ODDR_ALWAYS_LOW);
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ci->connectPort(id_XXX_VSS, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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ci->connectPort(id_ODDR_ALWAYS_LOW, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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ci->addInput(id_XXX_VCC);
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ci->addInput(id_ODDR_ALWAYS_HIGH);
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ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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ci->connectPort(id_ODDR_ALWAYS_HIGH, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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}
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}
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if (iob_bel != q0_dst->attrs.end()) {
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if (iob_bel != q0_dst->attrs.end()) {
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IdString io_bel_name = ctx->getBelByNameStr(iob_bel->second.as_string());
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IdString io_bel_name = ctx->getBelByNameStr(iob_bel->second.as_string());
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if (ctx->gw1n9_quirk && ctx->bels[io_bel_name].pins.count(id_XXX_VSS0)) {
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if (ctx->gw1n9_quirk && ctx->bels.at(io_bel_name).pins.count(id_GW9_ALWAYS_LOW0)) {
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q0_dst->disconnectPort(id_XXX_VSS0);
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q0_dst->disconnectPort(id_GW9_ALWAYS_LOW0);
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q0_dst->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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q0_dst->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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}
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}
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if (ctx->bels[io_bel_name].pins.count(id_XXX_1)) {
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if (ctx->bels.at(io_bel_name).pins.count(id_GW9C_ALWAYS_LOW1)) {
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q0_dst->disconnectPort(id_XXX_1);
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q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
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q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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}
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}
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}
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}
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} break;
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} break;
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@ -963,10 +963,10 @@ static void pack_iologic(Context *ctx)
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delete_nets.insert(ci->ports.at(output).net->name);
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delete_nets.insert(ci->ports.at(output).net->name);
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q0_dst->disconnectPort(id_I);
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q0_dst->disconnectPort(id_I);
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ci->disconnectPort(output);
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ci->disconnectPort(output);
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bool have_XXX = ctx->bels[ctx->getBelByNameStr(iob_bel->second.as_string())].pins.count(id_XXX_1);
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bool have_XXX = ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1);
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if (have_XXX) {
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if (have_XXX) {
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q0_dst->disconnectPort(id_XXX_1);
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q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
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q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
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}
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}
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// if Q1 is connected then disconnet it too
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// if Q1 is connected then disconnet it too
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@ -1287,11 +1287,11 @@ static void pack_io(Context *ctx)
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if (!constr_bel_name.empty()) {
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if (!constr_bel_name.empty()) {
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BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
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BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
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if (constr_bel != BelId()) {
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if (constr_bel != BelId()) {
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new_cell_type = ctx->bels[constr_bel].type;
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new_cell_type = ctx->bels.at(constr_bel).type;
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if (ctx->gw1n9_quirk) {
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if (ctx->gw1n9_quirk) {
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have_xxx_port = ctx->bels[constr_bel].pins.count(id_XXX_VSS0) != 0;
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have_xxx_port = ctx->bels.at(constr_bel).pins.count(id_GW9_ALWAYS_LOW0) != 0;
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}
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}
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have_xxx0_port = ctx->bels[constr_bel].pins.count(id_XXX_0) != 0;
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have_xxx0_port = ctx->bels.at(constr_bel).pins.count(id_GW9C_ALWAYS_LOW0) != 0;
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}
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}
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}
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}
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@ -1302,16 +1302,16 @@ static void pack_io(Context *ctx)
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auto gwiob = new_cells.back().get();
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auto gwiob = new_cells.back().get();
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// XXX GW1NR-9 quirks
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// XXX GW1NR-9 quirks
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if (have_xxx_port && ci->type != id_IBUF) {
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if (have_xxx_port && ci->type != id_IBUF) {
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gwiob->addInput(id_XXX_VSS0);
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gwiob->addInput(id_GW9_ALWAYS_LOW0);
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gwiob->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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gwiob->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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gwiob->addInput(id_XXX_VSS1);
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gwiob->addInput(id_GW9_ALWAYS_LOW1);
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gwiob->connectPort(id_XXX_VSS1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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gwiob->connectPort(id_GW9_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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}
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}
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if (have_xxx0_port && ci->type != id_IBUF) {
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if (have_xxx0_port && ci->type != id_IBUF) {
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gwiob->addInput(id_XXX_0);
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gwiob->addInput(id_GW9C_ALWAYS_LOW0);
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gwiob->connectPort(id_XXX_0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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gwiob->connectPort(id_GW9C_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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gwiob->addInput(id_XXX_1);
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gwiob->addInput(id_GW9C_ALWAYS_LOW1);
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gwiob->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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gwiob->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
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}
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}
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packed_cells.insert(ci->name);
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packed_cells.insert(ci->name);
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