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gowin: Rename questionable ports

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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2023-03-22 18:35:45 +10:00 committed by myrtle
parent 38eb1f05ff
commit c52906e8bc
3 changed files with 50 additions and 50 deletions
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40
gowin/arch.cc
View File

@ -420,7 +420,7 @@ void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
{
NPNR_ASSERT(bels.count(name) == 0);
NPNR_ASSERT(bel_by_loc.count(loc) == 0);
BelInfo &bi = bels[name];
BelInfo &bi = bels.at(name);
bi.name = name;
bi.type = type;
bi.x = loc.x;
@ -1572,23 +1572,23 @@ Arch::Arch(ArchArgs args) : args(args)
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_OEN, id(buf));
// GW1NR-9 quirk
const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS0);
if (xxx_port != nullptr) {
const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_GW9_ALWAYS_LOW0);
if (quirk_port != nullptr) {
gw1n9_quirk = true;
portname = IdString(xxx_port->src_id);
portname = IdString(quirk_port->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_XXX_VSS0, id(buf));
addBelInput(belname, id_GW9_ALWAYS_LOW0, id(buf));
}
xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS1);
if (xxx_port != nullptr) {
quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_GW9_ALWAYS_LOW1);
if (quirk_port != nullptr) {
gw1n9_quirk = true;
portname = IdString(xxx_port->src_id);
portname = IdString(quirk_port->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_XXX_VSS1, id(buf));
addBelInput(belname, id_GW9_ALWAYS_LOW1, id(buf));
}
if (!z && device_id == id("GW1NR-9C")) {
addBelInput(belname, id_XXX_0, idf("R%dC%d_C6", row + 1, col + 1));
addBelInput(belname, id_XXX_1, idf("R%dC%d_D6", row + 1, col + 1));
addBelInput(belname, id_GW9C_ALWAYS_LOW0, idf("R%dC%d_C6", row + 1, col + 1));
addBelInput(belname, id_GW9C_ALWAYS_LOW1, idf("R%dC%d_D6", row + 1, col + 1));
}
} break;
// Simplified IO
@ -1654,19 +1654,19 @@ Arch::Arch(ArchArgs args) : args(args)
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_CLK, id(buf));
const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS);
if (xxx_port != nullptr) {
const PairPOD *quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_LOW);
if (quirk_port != nullptr) {
ddr_has_extra_inputs = true;
portname = IdString(xxx_port->src_id);
portname = IdString(quirk_port->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_XXX_VSS, id(buf));
addBelInput(belname, id_ODDR_ALWAYS_LOW, id(buf));
}
xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VCC);
if (xxx_port != nullptr) {
quirk_port = pairLookup(bel->ports.get(), bel->num_ports, ID_ODDR_ALWAYS_HIGH);
if (quirk_port != nullptr) {
ddr_has_extra_inputs = true;
portname = IdString(xxx_port->src_id);
portname = IdString(quirk_port->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_XXX_VCC, id(buf));
addBelInput(belname, id_ODDR_ALWAYS_HIGH, id(buf));
}
if (oddrc) {
@ -2344,7 +2344,7 @@ void Arch::mark_used_hclk(Context *ctx)
log_info(" Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(this), user.port.c_str(this),
dstWire.c_str(this));
}
for (PipId const &pip : getPipsUphill(dstWire)) {
for (PipId pip : getPipsUphill(dstWire)) {
if (!checkPipAvail(pip)) {
WireId src_wire = getPipSrcWire(pip);
ci->setAttr(id_IOLOGIC_FCLK, Property(wire_info(src_wire).type.str(this)));

12
gowin/constids.inc
View File

@ -766,12 +766,12 @@ X(TX2)
X(TX3)
X(FCLK)
X(PCLK)
X(XXX_VSS)
X(XXX_VCC)
X(XXX_VSS0)
X(XXX_VSS1)
X(XXX_0)
X(XXX_1)
X(ODDR_ALWAYS_LOW)
X(ODDR_ALWAYS_HIGH)
X(GW9_ALWAYS_LOW0)
X(GW9_ALWAYS_LOW1)
X(GW9C_ALWAYS_LOW0)
X(GW9C_ALWAYS_LOW1)
X(OBUF_TYPE)
X(SBUF)
X(DBUF)

48
gowin/pack.cc
View File

@ -890,20 +890,20 @@ static void pack_iologic(Context *ctx)
}
// if have XXX_ inputs connect them
if (ctx->ddr_has_extra_inputs) {
ci->addInput(id_XXX_VSS);
ci->connectPort(id_XXX_VSS, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
ci->addInput(id_XXX_VCC);
ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
ci->addInput(id_ODDR_ALWAYS_LOW);
ci->connectPort(id_ODDR_ALWAYS_LOW, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
ci->addInput(id_ODDR_ALWAYS_HIGH);
ci->connectPort(id_ODDR_ALWAYS_HIGH, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
}
if (iob_bel != q0_dst->attrs.end()) {
IdString io_bel_name = ctx->getBelByNameStr(iob_bel->second.as_string());
if (ctx->gw1n9_quirk && ctx->bels[io_bel_name].pins.count(id_XXX_VSS0)) {
q0_dst->disconnectPort(id_XXX_VSS0);
q0_dst->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
if (ctx->gw1n9_quirk && ctx->bels.at(io_bel_name).pins.count(id_GW9_ALWAYS_LOW0)) {
q0_dst->disconnectPort(id_GW9_ALWAYS_LOW0);
q0_dst->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
}
if (ctx->bels[io_bel_name].pins.count(id_XXX_1)) {
q0_dst->disconnectPort(id_XXX_1);
q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
if (ctx->bels.at(io_bel_name).pins.count(id_GW9C_ALWAYS_LOW1)) {
q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
}
}
} break;
@ -963,10 +963,10 @@ static void pack_iologic(Context *ctx)
delete_nets.insert(ci->ports.at(output).net->name);
q0_dst->disconnectPort(id_I);
ci->disconnectPort(output);
bool have_XXX = ctx->bels[ctx->getBelByNameStr(iob_bel->second.as_string())].pins.count(id_XXX_1);
bool have_XXX = ctx->bels.at(ctx->getBelByNameStr(iob_bel->second.as_string())).pins.count(id_GW9C_ALWAYS_LOW1);
if (have_XXX) {
q0_dst->disconnectPort(id_XXX_1);
q0_dst->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
q0_dst->disconnectPort(id_GW9C_ALWAYS_LOW1);
q0_dst->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
}
// if Q1 is connected then disconnet it too
@ -1287,11 +1287,11 @@ static void pack_io(Context *ctx)
if (!constr_bel_name.empty()) {
BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
if (constr_bel != BelId()) {
new_cell_type = ctx->bels[constr_bel].type;
new_cell_type = ctx->bels.at(constr_bel).type;
if (ctx->gw1n9_quirk) {
have_xxx_port = ctx->bels[constr_bel].pins.count(id_XXX_VSS0) != 0;
have_xxx_port = ctx->bels.at(constr_bel).pins.count(id_GW9_ALWAYS_LOW0) != 0;
}
have_xxx0_port = ctx->bels[constr_bel].pins.count(id_XXX_0) != 0;
have_xxx0_port = ctx->bels.at(constr_bel).pins.count(id_GW9C_ALWAYS_LOW0) != 0;
}
}
@ -1302,16 +1302,16 @@ static void pack_io(Context *ctx)
auto gwiob = new_cells.back().get();
// XXX GW1NR-9 quirks
if (have_xxx_port && ci->type != id_IBUF) {
gwiob->addInput(id_XXX_VSS0);
gwiob->connectPort(id_XXX_VSS0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
gwiob->addInput(id_XXX_VSS1);
gwiob->connectPort(id_XXX_VSS1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
gwiob->addInput(id_GW9_ALWAYS_LOW0);
gwiob->connectPort(id_GW9_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
gwiob->addInput(id_GW9_ALWAYS_LOW1);
gwiob->connectPort(id_GW9_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
}
if (have_xxx0_port && ci->type != id_IBUF) {
gwiob->addInput(id_XXX_0);
gwiob->connectPort(id_XXX_0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
gwiob->addInput(id_XXX_1);
gwiob->connectPort(id_XXX_1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
gwiob->addInput(id_GW9C_ALWAYS_LOW0);
gwiob->connectPort(id_GW9C_ALWAYS_LOW0, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
gwiob->addInput(id_GW9C_ALWAYS_LOW1);
gwiob->connectPort(id_GW9C_ALWAYS_LOW1, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
}
packed_cells.insert(ci->name);