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ecp5: Global router produces a working bitstream

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-09-29 17:36:08 +01:00
parent c2a062d254
commit c5f9a12bb1
4 changed files with 17 additions and 0 deletions
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7
common/nextpnr.cc
View File

@ -99,8 +99,15 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
while (cursor != WireId() && cursor != src_wire) {
auto it = net_info->wires.find(cursor);
if (it == net_info->wires.end())
break;
#ifdef ARCH_ECP5
// ECP5 global nets currently appear part-unrouted due to arch database limitations
// Don't touch them in the router
if (it->second.strength == STRENGTH_LOCKED)
return 0;
#endif
PipId pip = it->second.pip;
delay += getPipDelay(pip).maxDelay();
delay += getWireDelay(cursor).maxDelay();

6
common/router1.cc
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@ -532,6 +532,12 @@ void addNetRouteJobs(Context *ctx, const Router1Cfg &cfg, IdString net_name,
{
NetInfo *net_info = ctx->nets.at(net_name).get();
#ifdef ARCH_ECP5
// ECP5 global nets currently appear part-unrouted due to arch database limitations
// Don't touch them in the router
if (!net_info->wires.empty() && net_info->wires.begin()->second.strength == STRENGTH_LOCKED)
return;
#endif
if (net_info->driver.cell == nullptr)
return;

2
ecp5/arch.cc
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@ -568,6 +568,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
if (port == id_O)
return TMG_STARTPOINT;
return TMG_IGNORE;
} else if (cell->type == id_DCCA) {
return TMG_IGNORE;
} else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
}

2
ecp5/bitstream.cc
View File

@ -294,6 +294,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
} else if (ci->type == ctx->id("DCCA")) {
// Nothing to do
} else {
NPNR_ASSERT_FALSE("unsupported cell type");
}