diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index b04679ad..d47a8525 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -99,8 +99,15 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
 
     while (cursor != WireId() && cursor != src_wire) {
         auto it = net_info->wires.find(cursor);
+
         if (it == net_info->wires.end())
             break;
+#ifdef ARCH_ECP5
+        // ECP5 global nets currently appear part-unrouted due to arch database limitations
+        // Don't touch them in the router
+        if (it->second.strength == STRENGTH_LOCKED)
+            return 0;
+#endif
         PipId pip = it->second.pip;
         delay += getPipDelay(pip).maxDelay();
         delay += getWireDelay(cursor).maxDelay();
diff --git a/common/router1.cc b/common/router1.cc
index 5cd4414c..d29cdd68 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -532,6 +532,12 @@ void addNetRouteJobs(Context *ctx, const Router1Cfg &cfg, IdString net_name,
 {
     NetInfo *net_info = ctx->nets.at(net_name).get();
 
+#ifdef ARCH_ECP5
+    // ECP5 global nets currently appear part-unrouted due to arch database limitations
+    // Don't touch them in the router
+    if (!net_info->wires.empty() && net_info->wires.begin()->second.strength == STRENGTH_LOCKED)
+        return;
+#endif
     if (net_info->driver.cell == nullptr)
         return;
 
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 861aeef2..1479e6ca 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -568,6 +568,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
         if (port == id_O)
             return TMG_STARTPOINT;
         return TMG_IGNORE;
+    } else if (cell->type == id_DCCA) {
+        return TMG_IGNORE;
     } else {
         NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
     }
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index a1edf9e5..f04b1269 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -294,6 +294,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
                 cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
             }
+        } else if (ci->type == ctx->id("DCCA")) {
+            // Nothing to do
         } else {
             NPNR_ASSERT_FALSE("unsupported cell type");
         }