ecp5: Fix FF timing data
Signed-off-by: David Shah <dave@ds0.me>
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c8cb9895a3
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@ -869,8 +869,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
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if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
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return TMG_COMB_OUTPUT;
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return TMG_COMB_OUTPUT;
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if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
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if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 0 && port == id_M0) ||
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(sd1 == 1 && port == id_M1)) {
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(sd1 == 0 && port == id_M1)) {
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clockInfoCount = 1;
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clockInfoCount = 1;
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return TMG_REGISTER_INPUT;
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return TMG_REGISTER_INPUT;
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}
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}
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@ -1037,8 +1037,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
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info.edge = RISING_EDGE;
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info.edge = RISING_EDGE;
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info.clock_port = id_WCK;
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info.clock_port = id_WCK;
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getSetupHoldFromTimingDatabase(id_SDPRAME, id_WCK, port, info.setup, info.hold);
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getSetupHoldFromTimingDatabase(id_SDPRAME, id_WCK, port, info.setup, info.hold);
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} else if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
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} else if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 0 && port == id_M0) ||
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(sd1 == 1 && port == id_M1)) {
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(sd1 == 0 && port == id_M1)) {
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info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
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info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
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info.clock_port = id_CLK;
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info.clock_port = id_CLK;
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getSetupHoldFromTimingDatabase(id_SLOGICB, id_CLK, port, info.setup, info.hold);
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getSetupHoldFromTimingDatabase(id_SLOGICB, id_CLK, port, info.setup, info.hold);
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