removed commented and not used code
This commit is contained in:
Miodrag Milanovic
myrtle
parent
3281ca6717
commit
c6f1f124f2
@ -432,7 +432,6 @@ bool Arch::route()
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disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
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assignArchInfo();
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assign_budget(getCtx(), true);
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bool result;
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if (router == "router1") {
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155
machxo2/pack.cc
155
machxo2/pack.cc
@ -1030,51 +1030,6 @@ class MachXO2Packer
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c->params[n] = c->params[o];
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c->params.erase(o);
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};
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/*for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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// Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
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if (ci->type == id_PDPW8KC) {
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ci->params[id_DATA_WIDTH_A] = 18; // force PDP mode
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ci->params.erase(id_DATA_WIDTH_W);
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rename_bus(ci, "BE", "ADA", 4, 0, 0);
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rename_bus(ci, "ADW", "ADA", 9, 0, 5);
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rename_bus(ci, "ADR", "ADB", 14, 0, 0);
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rename_bus(ci, "CSW", "CSA", 3, 0, 0);
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rename_bus(ci, "CSR", "CSB", 3, 0, 0);
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rename_bus(ci, "DI", "DIA", 18, 0, 0);
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rename_bus(ci, "DI", "DIB", 18, 18, 0);
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rename_bus(ci, "DO", "DOA", 18, 18, 0);
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rename_bus(ci, "DO", "DOB", 18, 0, 0);
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ci->renamePort(id_CLKW, id_CLKA);
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ci->renamePort(id_CLKR, id_CLKB);
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ci->renamePort(id_CEW, id_CEA);
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ci->renamePort(id_CER, id_CEB);
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ci->renamePort(id_OCER, id_OCEB);
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rename_param(ci, "CLKWMUX", "CLKAMUX");
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if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
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ci->params[id_CLKAMUX] = std::string("CLKA");
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rename_param(ci, "CLKRMUX", "CLKBMUX");
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if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
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ci->params[id_CLKBMUX] = std::string("CLKB");
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rename_param(ci, "CSDECODE_W", "CSDECODE_A");
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rename_param(ci, "CSDECODE_R", "CSDECODE_B");
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std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
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ci->params[id_REGMODE_A] = outreg;
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ci->params[id_REGMODE_B] = outreg;
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ci->params.erase(id_REGMODE);
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rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
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if (ci->ports.count(id_RST)) {
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autocreate_empty_port(ci, id_RSTA);
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autocreate_empty_port(ci, id_RSTB);
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NetInfo *rst = ci->ports.at(id_RST).net;
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ci->connectPort(id_RSTA, rst);
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ci->connectPort(id_RSTB, rst);
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ci->disconnectPort(id_RST);
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ci->ports.erase(id_RST);
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}
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ci->type = id_DP8KC;
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}
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}*/
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type == id_DP8KC) {
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@ -1340,113 +1295,8 @@ class MachXO2Packer
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changed_nets.clear();
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for (auto cell : changed_cells) {
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CellInfo *ci = ctx->cells.at(cell).get();
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/* if (ci->type == id_CLKDIVF) {
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std::string div = str_or_default(ci->params, id_DIV, "2.0");
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double ratio;
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if (div == "2.0")
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ratio = 1 / 2.0;
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else if (div == "3.5")
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ratio = 1 / 3.5;
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else
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log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
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copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
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} else if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) {
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copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
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} else if (ci->type == id_ECLKBRIDGECS) {
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copy_constraint(ci, id_CLK0, id_ECSOUT, 1);
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copy_constraint(ci, id_CLK1, id_ECSOUT, 1);
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} else */
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if (ci->type == id_DCCA) {
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copy_constraint(ci, id_CLKI, id_CLKO, 1);
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/*} else if (ci->type == id_DCSC) {
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if ((!ci->ports.count(id_CLK0) && !ci->ports.count(id_CLK1)) || !ci->ports.count(id_DCSOUT))
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continue;
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auto mode = str_or_default(ci->params, id_DCSMODE, "POS");
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bool mode_constant = false;
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auto mode_is_constant = net_is_constant(ctx, ci->ports.at(id_MODESEL).net, mode_constant);
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if (mode_is_constant && mode_constant == false) {
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if (mode == "CLK0_LOW" || mode == "CLK0_HIGH" || mode == "CLK0") {
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copy_constraint(ci, id_CLK0, id_DCSOUT, 1.0);
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continue;
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} else if (mode == "CLK1_LOW" || mode == "CLK1_HIGH" || mode == "CLK1") {
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copy_constraint(ci, id_CLK1, id_DCSOUT, 1.0);
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continue;
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} else if (mode == "LOW" || mode == "HIGH") {
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continue;
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}
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}
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std::unique_ptr<ClockConstraint> derived_constr = nullptr;
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std::vector<NetInfo *> in_ports = {
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ci->ports.at(id_CLK0).net,
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ci->ports.at(id_CLK1).net,
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};
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// Generate all unique clock pairs find the worst
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// constraint from switching between them and merge them
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// into the final output constraint.
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for (size_t i = 0; i < in_ports.size(); ++i) {
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auto p1 = in_ports[i];
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if (p1 == nullptr || p1->clkconstr == nullptr) {
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derived_constr = nullptr;
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break;
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}
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for (size_t j = i + 1; j < in_ports.size(); ++j) {
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auto p2 = in_ports[j];
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if (p2 == nullptr || p2->clkconstr == nullptr) {
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break;
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}
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auto &c1 = p1->clkconstr;
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auto &c2 = p2->clkconstr;
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auto merged_constr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
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if (mode == "NEG") {
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merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
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std::max(c1->low.max_delay + c2->period.max_delay,
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c2->low.max_delay + c1->period.max_delay));
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} else {
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merged_constr->low = DelayPair(std::min(c1->low.min_delay, c2->low.min_delay),
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std::max(c1->low.max_delay, c2->low.max_delay));
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}
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if (mode == "POS") {
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merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
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std::max(c1->high.max_delay + c2->period.max_delay,
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c2->high.max_delay + c1->period.max_delay));
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} else {
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merged_constr->high = DelayPair(std::min(c1->high.min_delay, c2->high.min_delay),
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std::max(c1->high.max_delay, c2->high.max_delay));
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}
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merged_constr->period = DelayPair(std::min(c1->period.min_delay, c2->period.min_delay),
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std::max(c1->period.max_delay, c2->period.max_delay));
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if (derived_constr == nullptr) {
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derived_constr = std::move(merged_constr);
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continue;
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}
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derived_constr->period.min_delay =
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std::min(derived_constr->period.min_delay, merged_constr->period.min_delay);
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derived_constr->period.max_delay =
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std::max(derived_constr->period.max_delay, merged_constr->period.max_delay);
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derived_constr->low.min_delay =
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std::min(derived_constr->low.min_delay, merged_constr->low.min_delay);
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derived_constr->low.max_delay =
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std::max(derived_constr->low.max_delay, merged_constr->low.max_delay);
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derived_constr->high.min_delay =
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std::min(derived_constr->high.min_delay, merged_constr->high.min_delay);
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derived_constr->high.max_delay =
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std::max(derived_constr->high.max_delay, merged_constr->high.max_delay);
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}
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}
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if (derived_constr != nullptr) {
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set_constraint(ci, id_DCSOUT, std::move(derived_constr));
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}*/
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} else if (ci->type == id_EHXPLLJ) {
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delay_t period_in;
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if (!get_period(ci, id_CLKI, period_in))
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@ -1483,10 +1333,7 @@ class MachXO2Packer
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simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
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set_constraint(ci, id_CLKOS3,
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simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
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}/* else if (ci->type == id_OSCH) {
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int div = int_or_default(ci->params, id_DIV, 128);
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set_constraint(ci, id_OSC, simple_clk_contraint(delay_t((1.0e6 / (2.0 * 155)) * div)));
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}*/
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}
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}
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}
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}
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