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Adapt blinky for xc7

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This commit is contained in:
Eddie Hung 2018-11-09 17:05:55 -08:00
parent 11b1309e62
commit c6f66b4468
3 changed files with 18 additions and 17 deletions
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2
xc7/blinky.pcf
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@ -4,3 +4,5 @@ COMP "led2" LOCATE = SITE "G14" LEVEL 1;
COMP "led3" LOCATE = SITE "D18" LEVEL 1;
COMP "clki" LOCATE = SITE "K17" LEVEL 1;
NET "clki" PERIOD = 8 nS ;
PIN "clki_pin" = BEL "clki$iob.PAD" PINNAME PAD;
PIN "clki_pin" CLOCK_DEDICATED_ROUTE = FALSE;

9
xc7/blinky.sh
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@ -3,9 +3,8 @@ set -ex
yosys blinky.ys
../nextpnr-xc7 --json blinky.json --pcf blinky.pcf --xdl blinky.xdl --freq 250
xdl -xdl2ncd blinky.xdl
trce blinky.ncd -v 10
bitgen -w blinky.ncd -g UnconstrainedPins:Allow
#icepack blinky.asc blinky.bin
#icebox_vlog blinky.asc > blinky_chip.v
#iverilog -o blinky_tb blinky_chip.v blinky_tb.v
#vvp -N ./blinky_tb
trce blinky.ncd -v 10
netgen -ofmt verilog -w blinky.ncd blinky_chip.v -tm blinky
iverilog -o blinky_tb blinky_chip.v blinky_tb.v -y/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/ -insert_glbl true
vvp -N ./blinky_tb

24
xc7/blinky_tb.v
View File

@ -2,24 +2,24 @@ module blinky_tb;
reg clk;
always #5 clk = (clk === 1'b0);
wire led1, led2, led3, led4, led5;
wire led0, led1, led2, led3;
chip uut (
.io_0_8_1(clk),
.io_13_12_1(led1),
.io_13_12_0(led2),
.io_13_11_1(led3),
.io_13_11_0(led4),
.io_13_9_1(led5)
.\clki$iob.PAD.PAD (clk),
.\led0$iob.OUTBUF.OUT (led0),
.\led1$iob.OUTBUF.OUT (led1),
.\led2$iob.OUTBUF.OUT (led2),
.\led3$iob.OUTBUF.OUT (led3)
);
initial begin
// $dumpfile("blinky_tb.vcd");
// $dumpvars(0, blinky_tb);
repeat (10) begin
repeat (900000) @(posedge clk);
$display(led1, led2, led3, led4, led5);
end
$finish;
$monitor(led0, led1, led2, led3);
//repeat (10) begin
// repeat (900000) @(posedge clk);
// $display(led0, led1, led2, led3);
//end
//$finish;
end
endmodule