caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge pull request #309 from YosysHQ/dsptiming

Browse Source 
ecp5: Conservative analysis of comb DSP timing
This commit is contained in:
David Shah 2019-08-09 10:27:15 +01:00 committed by GitHub
commit c70f87e4c5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 25 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
ecp5/arch.cc
View File

@ -707,6 +707,13 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
return false;
} else if (cell->type == id_DP16KD) {
return false;
} else if (cell->type == id_MULT18X18D) {
std::string fn = fromPort.str(this), tn = toPort.str(this);
if (fn.size() > 1 && (fn.front() == 'A' || fn.front() == 'B') && std::isdigit(fn.at(1))) {
if (tn.size() > 1 && tn.front() == 'P' && std::isdigit(tn.at(1)))
return getDelayFromTimingDatabase(id_MULT18X18D_REGS_NONE, id(std::string("") + fn.front()), id_P, delay);
}
return false;
} else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
return false;
} else {
@ -784,7 +791,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
}
NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
} else if (cell->type == id_MULT18X18D) {
return TMG_IGNORE; // FIXME
if (port == id_CLK0 || port == id_CLK1 || port == id_CLK2 || port == id_CLK3)
return TMG_CLOCK_INPUT;
std::string pname = port.str(this);
if (pname.size() > 1) {
if ((pname.front() == 'A' || pname.front() == 'B') && std::isdigit(pname.at(1)))
return TMG_COMB_INPUT;
if (pname.front() == 'P' && std::isdigit(pname.at(1)))
return TMG_COMB_OUTPUT;
}
return TMG_IGNORE;
} else if (cell->type == id_ALU54B) {
return TMG_IGNORE; // FIXME
} else if (cell->type == id_EHXPLLL) {

9
ecp5/constids.inc
View File

@ -1281,4 +1281,11 @@ X(RDCFLAG)
X(WRCFLAG)
X(SCLK)
X(TRELLIS_ECLKBUF)
X(TRELLIS_ECLKBUF)
X(MULT18X18D_REGS_ALL)
X(MULT18X18D_REGS_INPUT)
X(MULT18X18D_REGS_NONE)
X(MULT18X18D_REGS_OUTPUT)
X(MULT18X18D_REGS_PIPELINE)
X(P)