nexus: Add iterator types based on nextpnr-xilinx
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
60c6510b3b
commit
c7f00b4760
371
nexus/arch.h
371
nexus/arch.h
@ -162,6 +162,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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RelPtr<char> device_name;
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uint16_t width;
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uint16_t height;
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uint32_t num_tiles;
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RelPtr<GridLocationPOD> grid;
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});
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@ -174,6 +175,330 @@ NPNR_PACKED_STRUCT(struct DatabasePOD {
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RelPtr<LocTypePOD> loctypes;
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});
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// -----------------------------------------------------------------------
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// Helper functions for database access
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namespace {
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template <typename Id> const LocTypePOD &chip_loc_data(const DatabasePOD *db, const ChipInfoPOD *chip, Id &id)
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{
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return db->loctypes[chip->grid[id.tile].loc_type];
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}
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template <typename Id> const LocNeighourhoodPOD &chip_nh_data(const DatabasePOD *db, const ChipInfoPOD *chip, Id &id)
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{
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auto &t = chip->grid[id.tile];
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return db->loctypes[t.loc_type].neighbourhoods[t.neighbourhood_type];
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}
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inline const BelInfoPOD &chip_bel_data(const DatabasePOD *db, const ChipInfoPOD *chip, BelId id)
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{
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return chip_loc_data(db, chip, id).bels[id.index];
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}
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inline const LocWireInfoPOD &chip_wire_data(const DatabasePOD *db, const ChipInfoPOD *chip, WireId &id)
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{
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return chip_loc_data(db, chip, id).wires[id.index];
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}
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inline const PipInfoPOD &chip_pip_data(const DatabasePOD *db, const ChipInfoPOD *chip, PipId &id)
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{
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return chip_loc_data(db, chip, id).pips[id.index];
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}
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inline bool chip_rel_tile(const ChipInfoPOD *chip, int32_t base, int16_t rel_x, int16_t rel_y, int32_t &next)
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{
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int32_t curr_x = base % chip->width;
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int32_t curr_y = base / chip->width;
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int32_t new_x = curr_x + rel_x;
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int32_t new_y = curr_y + rel_y;
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if (new_x < 0 || new_x >= chip->width)
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return false;
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if (new_y < 0 || new_y >= chip->height)
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return false;
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next = new_y * chip->width + new_x;
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return true;
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}
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inline WireId chip_canonical_wire(const DatabasePOD *db, const ChipInfoPOD *chip, int32_t tile, uint16_t index)
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{
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WireId wire{tile, index};
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// `tile` is the primary location for the wire, so ID is already canonical
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if (chip_wire_data(db, chip, wire).flags & WIRE_PRIMARY)
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return wire;
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// Not primary; find the primary location which forms the canonical ID
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auto &nd = chip_nh_data(db, chip, wire);
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auto &wn = nd.wire_neighbours[index];
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for (size_t i = 0; i < wn.num_nwires; i++) {
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auto &nw = wn.neigh_wires[i];
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if (nw.arc_flags & LOGICAL_TO_PRIMARY) {
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if (chip_rel_tile(chip, tile, nw.rel_x, nw.rel_y, wire.tile)) {
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wire.index = nw.wire_index;
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break;
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}
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}
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}
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return wire;
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}
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inline bool chip_wire_is_primary(const DatabasePOD *db, const ChipInfoPOD *chip, int32_t tile, uint16_t index)
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{
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WireId wire{tile, index};
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// `tile` is the primary location for the wire, so ID is already canonical
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if (chip_wire_data(db, chip, wire).flags & WIRE_PRIMARY)
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return true;
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// Not primary; find the primary location which forms the canonical ID
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auto &nd = chip_nh_data(db, chip, wire);
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auto &wn = nd.wire_neighbours[index];
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for (size_t i = 0; i < wn.num_nwires; i++) {
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auto &nw = wn.neigh_wires[i];
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if (nw.arc_flags & LOGICAL_TO_PRIMARY) {
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if (chip_rel_tile(chip, tile, nw.rel_x, nw.rel_y, wire.tile)) {
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return false;
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}
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}
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}
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return true;
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}
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} // namespace
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// -----------------------------------------------------------------------
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struct BelIterator
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{
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const DatabasePOD *db;
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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BelIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < int(chip->num_tiles) &&
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cursor_index >= int(db->loctypes[chip->grid[cursor_tile].loc_type].num_bels)) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const BelIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const BelIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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BelId operator*() const
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{
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BelId ret;
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ret.tile = cursor_tile;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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const DatabasePOD *db;
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile = 0;
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WireIterator operator++()
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{
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// Iterate over nodes first, then tile wires that aren't nodes
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do {
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cursor_index++;
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while (cursor_tile < int(chip->num_tiles) &&
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cursor_index >= int(db->loctypes[chip->grid[cursor_tile].loc_type].num_wires)) {
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cursor_index = 0;
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cursor_tile++;
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}
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} while (cursor_tile < int(chip->num_tiles) && !chip_wire_is_primary(db, chip, cursor_tile, cursor_index));
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return *this;
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}
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WireIterator operator++(int)
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{
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WireIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const WireIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const WireIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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WireId operator*() const
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{
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WireId ret;
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ret.tile = cursor_tile;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// Iterate over all neighour wires for a wire
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struct TileWireIterator
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{
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const DatabasePOD *db;
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const ChipInfoPOD *chip;
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WireId baseWire;
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int cursor = -1;
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void operator++()
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{
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auto &wn = chip_nh_data(db, chip, baseWire).wire_neighbours[baseWire.index];
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int32_t tile;
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do
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cursor++;
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while (cursor < int(wn.num_nwires) &&
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((wn.neigh_wires[cursor].arc_flags & LOGICAL_TO_PRIMARY) ||
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!chip_rel_tile(chip, baseWire.tile, wn.neigh_wires[cursor].rel_x, wn.neigh_wires[cursor].rel_y, tile)));
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}
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bool operator!=(const TileWireIterator &other) const { return cursor != other.cursor; }
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// Returns a *denormalised* identifier that may be a non-primary wire (and thus should _not_ be used
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// as a WireId in general as it will break invariants)
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WireId operator*() const
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{
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if (cursor == -1) {
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return baseWire;
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} else {
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auto &nw = chip_nh_data(db, chip, baseWire).wire_neighbours[baseWire.index].neigh_wires[cursor];
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WireId result;
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result.index = nw.wire_index;
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if (!chip_rel_tile(chip, baseWire.tile, nw.rel_x, nw.rel_y, result.tile))
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return WireId();
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return result;
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}
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}
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};
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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const DatabasePOD *db;
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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AllPipIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < int(chip->num_tiles) &&
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cursor_index >= int(db->loctypes[chip->grid[cursor_tile].loc_type].num_pips)) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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AllPipIterator operator++(int)
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{
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AllPipIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const AllPipIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const AllPipIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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PipId operator*() const
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{
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PipId ret;
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ret.tile = cursor_tile;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct UpDownhillPipIterator
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{
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const DatabasePOD *db;
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const ChipInfoPOD *chip;
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TileWireIterator twi, twi_end;
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int cursor = -1;
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bool uphill = false;
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void operator++()
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{
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cursor++;
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while (true) {
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if (!(twi != twi_end))
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break;
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WireId w = *twi;
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auto &tile = db->loctypes[chip->grid[w.tile].loc_type];
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if (cursor < int(uphill ? tile.wires[w.index].num_uphill : tile.wires[w.index].num_downhill))
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break;
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++twi;
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cursor = 0;
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}
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}
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bool operator!=(const UpDownhillPipIterator &other) const { return twi != other.twi || cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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WireId w = *twi;
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ret.tile = w.tile;
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auto &tile = db->loctypes[chip->grid[w.tile].loc_type];
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ret.index = uphill ? tile.wires[w.index].pips_uh[cursor] : tile.wires[w.index].pips_dh[cursor];
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return ret;
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}
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};
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struct UpDownhillPipRange
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{
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UpDownhillPipIterator b, e;
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UpDownhillPipIterator begin() const { return b; }
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UpDownhillPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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const int bba_version =
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#include "bba_version.inc"
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;
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@ -205,52 +530,20 @@ struct Arch : BaseCtx
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int getTileBelDimZ(int, int) const { return 256; }
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int getTilePipDimZ(int, int) const { return 1; }
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template <typename Id> const LocTypePOD &loc_data(Id &id) const
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{
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return db->loctypes[chip_info->grid[id.tile].loc_type];
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}
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template <typename Id> const LocTypePOD &loc_data(Id &id) const { return chip_loc_data(db, chip_info, id); }
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template <typename Id> const LocNeighourhoodPOD &nh_data(Id &id) const
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{
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auto &t = chip_info->grid[id.tile];
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return db->loctypes[t.loc_type].neighbourhoods[t.neighbourhood_type];
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}
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template <typename Id> const LocNeighourhoodPOD &nh_data(Id &id) const { return chip_nh_data(db, chip_info, id); }
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inline const BelInfoPOD &bel_data(BelId id) const { return loc_data(id).bels[id.index]; }
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inline const LocWireInfoPOD &wire_data(WireId &id) const { return loc_data(id).wires[id.index]; }
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inline const PipInfoPOD &pip_data(PipId &id) const { return loc_data(id).pips[id.index]; }
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inline const BelInfoPOD &bel_data(BelId id) const { return chip_bel_data(db, chip_info, id); }
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inline const LocWireInfoPOD &wire_data(WireId &id) const { return chip_wire_data(db, chip_info, id); }
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inline const PipInfoPOD &pip_data(PipId &id) const { return chip_pip_data(db, chip_info, id); }
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inline bool rel_tile(int32_t base, int16_t rel_x, int16_t rel_y, int32_t &next)
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{
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int32_t curr_x = base % chip_info->width;
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int32_t curr_y = base / chip_info->width;
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int32_t new_x = curr_x + rel_x;
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int32_t new_y = curr_y + rel_y;
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if (new_x < 0 || new_x >= chip_info->width)
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return false;
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if (new_y < 0 || new_y >= chip_info->height)
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return false;
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next = new_y * chip_info->width + new_x;
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return true;
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return chip_rel_tile(chip_info, base, rel_x, rel_y, next);
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}
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inline const WireId canonical_wire(int32_t tile, uint16_t index)
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{
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WireId wire{tile, index};
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// `tile` is the primary location for the wire, so ID is already canonical
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if (wire_data(wire).flags & WIRE_PRIMARY)
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return wire;
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// Not primary; find the primary location which forms the canonical ID
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auto &nd = nh_data(wire);
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auto &wn = nd.wire_neighbours[index];
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for (size_t i = 0; i < wn.num_nwires; i++) {
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auto &nw = wn.neigh_wires[i];
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if (nw.arc_flags & LOGICAL_TO_PRIMARY) {
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if (rel_tile(tile, nw.rel_x, nw.rel_y, wire.tile)) {
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wire.index = nw.wire_index;
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break;
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}
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}
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}
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return wire;
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return chip_canonical_wire(db, chip_info, tile, index);
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}
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};
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