gowin: Himbaechel. Add a wideluts
- MUX2_LUT5, MUX2_LUT6, MUX2_LUT7 and MUX2_LUT8 support; - storing a common class of files in extra_data; - misc fixes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit
myrtle
parent
f7fbe0db04
commit
c82654d003
@ -19,17 +19,7 @@ void GowinImpl::init(Context *ctx)
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// Arch::archArgsToId
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}
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void GowinImpl::prePlace()
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{
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ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
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ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
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ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
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assign_cell_info();
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}
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void GowinImpl::prePlace() { assign_cell_info(); }
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void GowinImpl::pack()
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{
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@ -47,15 +37,17 @@ void GowinImpl::pack()
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// disconnect the constant LUT inputs
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mod_lut_inputs();
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pack_wideluts();
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// Constrain directly connected LUTs and FFs together to use dedicated resources
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int lutffs = h.constrain_cell_pairs(
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pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
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pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
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{id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
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{id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
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{id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
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{id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},
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1);
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auto lut_outs = pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}};
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auto dff_ins = pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
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{id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
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{id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
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{id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
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{id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
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int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1);
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log_info("Constrained %d LUTFF pairs.\n", lutffs);
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}
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@ -237,4 +229,101 @@ void GowinImpl::mod_lut_inputs(void)
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}
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}
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// make cluster from LUTs and MUXes
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void GowinImpl::pack_wideluts(void)
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{
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// children's offsets
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struct _children
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{
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IdString port;
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int dx, dz;
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} mux_inputs[4][2] = {{{id_I0, 1, -7}, {id_I1, 0, -7}},
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{{id_I0, 0, 4}, {id_I1, 0, -4}},
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{{id_I0, 0, 2}, {id_I1, 0, -2}},
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{{id_I0, 0, -BelZ::MUX20_Z}, {id_I1, 0, 2 - BelZ::MUX20_Z}}};
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typedef std::function<void(CellInfo &, CellInfo *, int, int)> recurse_func_t;
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recurse_func_t make_cluster = [&, this](CellInfo &ci_root, CellInfo *ci_cursor, int dx, int dz) {
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_children *inputs;
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if (is_lut(ci_cursor)) {
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return;
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}
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switch (ci_cursor->type.hash()) {
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case ID_MUX2_LUT8:
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inputs = mux_inputs[0];
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break;
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case ID_MUX2_LUT7:
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inputs = mux_inputs[1];
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break;
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case ID_MUX2_LUT6:
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inputs = mux_inputs[2];
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break;
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case ID_MUX2_LUT5:
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inputs = mux_inputs[3];
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break;
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default:
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log_error("Bad MUX2 node:%s\n", ctx->nameOf(ci_cursor));
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}
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for (int i = 0; i < 2; ++i) {
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// input src
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NetInfo *in = ci_cursor->getPort(inputs[i].port);
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NPNR_ASSERT(in && in->driver.cell);
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int child_dx = dx + inputs[i].dx;
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int child_dz = dz + inputs[i].dz;
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ci_root.constr_children.push_back(in->driver.cell);
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in->driver.cell->cluster = ci_root.name;
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in->driver.cell->constr_abs_z = false;
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in->driver.cell->constr_x = child_dx;
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in->driver.cell->constr_y = 0;
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in->driver.cell->constr_z = child_dz;
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make_cluster(ci_root, in->driver.cell, child_dx, child_dz);
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}
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};
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// look for MUX2
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// MUX2_LUT8 create right away, collect others
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std::vector<IdString> muxes[3];
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int packed[4] = {0, 0, 0, 0};
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for (auto &cell : ctx->cells) {
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auto &ci = *cell.second;
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if (ci.cluster != ClusterId()) {
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continue;
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}
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if (ci.type == id_MUX2_LUT8) {
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ci.cluster = ci.name;
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ci.constr_abs_z = 0;
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make_cluster(ci, &ci, 0, 0);
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++packed[0];
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continue;
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}
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if (ci.type.in(id_MUX2_LUT7, id_MUX2_LUT6, id_MUX2_LUT5)) {
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switch (ci.type.hash()) {
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case ID_MUX2_LUT7:
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muxes[0].push_back(cell.first);
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break;
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case ID_MUX2_LUT6:
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muxes[1].push_back(cell.first);
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break;
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default: // ID_MUX2_LUT5
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muxes[2].push_back(cell.first);
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break;
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}
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}
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}
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// create others
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for (int i = 0; i < 3; ++i) {
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for (IdString cell_name : muxes[i]) {
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auto &ci = *ctx->cells.at(cell_name);
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if (ci.cluster != ClusterId()) {
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continue;
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}
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ci.cluster = ci.name;
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ci.constr_abs_z = 0;
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make_cluster(ci, &ci, 0, 0);
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++packed[i + 1];
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}
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}
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log_info("Packed MUX2_LUT8:%d, MUX2_LU7:%d, MUX2_LUT6:%d, MUX2_LUT5:%d\n", packed[0], packed[1], packed[2],
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packed[3]);
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}
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NEXTPNR_NAMESPACE_END
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@ -45,6 +45,8 @@ struct GowinImpl : HimbaechelAPI
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// modify LUTs with constant inputs
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void mod_lut_inputs(void);
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void pack_wideluts(void);
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// Return true if a cell is a LUT
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inline bool type_is_lut(IdString cell_type) const { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
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inline bool is_lut(const CellInfo *cell) const { return type_is_lut(cell->type); }
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@ -68,5 +70,21 @@ struct GowinArch : HimbaechelArch
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} exampleArch;
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} // namespace
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// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
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namespace BelZ {
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enum
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{
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LUT0_Z = 0,
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LUT7_Z = 14,
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MUX20_Z = 16,
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MUX21_Z = 18,
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MUX23_Z = 22,
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MUX27_Z = 29,
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VCC_Z = 277,
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VSS_Z = 278
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};
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}
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NEXTPNR_NAMESPACE_END
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#endif
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@ -12,8 +12,27 @@ from himbaechel_dbgen.chip import *
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from apycula import chipdb
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# Z of the bels
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VCC_Z = 277
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GND_Z = 288
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# sync with C++ part!
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LUT0_Z = 0 # z(DFFx) = z(LUTx) + 1
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LUT7_Z = 14
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MUX20_Z = 16
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MUX21_Z = 18
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MUX23_Z = 22
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MUX27_Z = 29
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VCC_Z = 277
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GND_Z = 278
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@dataclass
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class TileExtraData(BBAStruct):
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tile_class: IdString # The general functionality of the slightly different tiles,
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# let's say the behavior of LUT+DFF in the tiles are completely identical,
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# but one of them also contains clock-wire switches,
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# then we assign them to the same LOGIC class.
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.tile_class.index)
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created_tiletypes = set()
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@ -72,6 +91,10 @@ def create_nodes(chip: Chip, db: chipdb):
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nodes.append([NodeWire(x, y, f'{d}8{i}0'),
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NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
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NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
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# I0 for MUX2_LUT8
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if x < X - 1 and chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC') and chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC'):
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nodes.append([NodeWire(x, y, 'OF30'),
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NodeWire(x + 1, y, 'OF3')])
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for node in nodes:
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chip.add_node(node)
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# VCC and VSS sources in the all tiles
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@ -99,7 +122,9 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp
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tt = chip.create_tile_type(f"NULL_{ttyp}")
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typename = "NULL"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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create_switch_matrix(tt, db, x, y)
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return ttyp
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@ -107,7 +132,9 @@ def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp
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tt = chip.create_tile_type(f"CORNER_{ttyp}")
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typename = "CORNER"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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if x == 0 and y == 0:
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# GND is the logic low level generator
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@ -126,7 +153,10 @@ def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp
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tt = chip.create_tile_type(f"IO_{ttyp}")
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typename = "IO"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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for i in range(2):
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name = ['IOBA', 'IOBB'][i]
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# wires
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@ -142,13 +172,15 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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# XXX lut+dff only for now
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def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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N = 8
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lut_inputs = ['A', 'B', 'C', 'D']
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if ttyp in created_tiletypes:
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return ttyp
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tt = chip.create_tile_type(f"LOGIC_{ttyp}")
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typename = "LOGIC"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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# setup wires
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for i in range(N):
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for i in range(8):
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for inp_name in lut_inputs:
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tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
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tt.create_wire(f"F{i}", "LUT_OUT")
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@ -162,9 +194,13 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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tt.create_wire(f"CLK{j}", "TILE_CLK")
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tt.create_wire(f"LSR{j}", "TILE_LSR")
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tt.create_wire(f"CE{j}", "TILE_CE")
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for j in range(8):
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tt.create_wire(f"OF{j}", "MUX_OUT")
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tt.create_wire(f"SEL{j}", "MUX_SEL")
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tt.create_wire("OF30", "MUX_OUT")
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# create logic cells
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for i in range(N):
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for i in range(8):
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# LUT
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lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0))
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for j, inp_name in enumerate(lut_inputs):
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@ -186,6 +222,30 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
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# wide luts
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for i in range(4):
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ff = tt.create_bel(f"MUX{i * 2}", "MUX2_LUT5", z = MUX20_Z + i * 4)
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tt.add_bel_pin(ff, "I0", f"F{i * 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"F{i * 2 + 1}", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF{i * 2}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL{i * 2}", PinType.INPUT)
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for i in range(2):
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ff = tt.create_bel(f"MUX{i * 4 + 1}", "MUX2_LUT6", z = MUX21_Z + i * 8)
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tt.add_bel_pin(ff, "I0", f"OF{i * 4 + 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF{i * 4}", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF{i * 4 + 1}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL{i * 4 + 1}", PinType.INPUT)
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ff = tt.create_bel(f"MUX3", "MUX2_LUT7", z = MUX23_Z)
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tt.add_bel_pin(ff, "I0", f"OF5", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF1", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF3", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL3", PinType.INPUT)
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ff = tt.create_bel(f"MUX7", "MUX2_LUT8", z = MUX27_Z)
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tt.add_bel_pin(ff, "I0", f"OF30", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF3", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF7", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
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create_switch_matrix(tt, db, x, y)
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return ttyp
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@ -212,7 +272,7 @@ def main():
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# these differences (in case it turns out later that there is a slightly
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# different routing or something like that).
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logic_tiletypes = {12, 13, 14, 15, 16, 17}
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io_tiletypes = {53, 58, 64} # Tangnano9k leds tiles and clock ;)
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io_tiletypes = {53, 55, 58, 59, 64, 65}
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# Setup tile grid
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for x in range(X):
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for y in range(Y):
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