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xilinx: Filter out another missing pip type

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2024-09-26 15:56:20 +02:00
parent 437fb70ed3
commit c90d872e35
1 changed files with 2 additions and 0 deletions
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2
himbaechel/uarch/xilinx/gen/filters.py
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@ -91,6 +91,8 @@ def include_pip(tile_type, p):
if tile_type.startswith("HCLK_IOI"):
if "RCLK_BEFORE_DIV" in p.dst_wire().name() and "IMUX" in p.src_wire().name():
return False
if p.dst_wire().name().endswith("_DMUX") and "I2IOCLK_TOP" in p.src_wire().name():
return False
if "IOI" in tile_type:
if "CLKB" in p.dst_wire().name() and "IMUX22" in p.src_wire().name():
return False