pnr runs1111
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@ -332,8 +332,8 @@ const GlobalAliasPOD* aliasLookup(const GlobalAliasPOD *first, int len, const Gl
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Arch::Arch(ArchArgs args) : args(args)
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Arch::Arch(ArchArgs args) : args(args)
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{
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{
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family = "GW1N-9";
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family = "GW1N-1";
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device = "GW1N-9";
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device = "GW1N-1";
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speed = "C6/E5"; // or whatever
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speed = "C6/E5"; // or whatever
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package = "QFN48"; // or something
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package = "QFN48"; // or something
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@ -461,11 +461,11 @@ Arch::Arch(ArchArgs args) : args(args)
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portname = pairLookup(bel->ports.get(), bel->num_ports, -1, ID_O)->src_id;
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portname = pairLookup(bel->ports.get(), bel->num_ports, -1, ID_O)->src_id;
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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wirename = id(buf);
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wirename = id(buf);
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addBelInput(belname, id_I, wirename);
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addBelOutput(belname, id_O, wirename);
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portname = pairLookup(bel->ports.get(), bel->num_ports, -1, ID_O)->src_id;
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portname = pairLookup(bel->ports.get(), bel->num_ports, -1, ID_I)->src_id;
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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wirename = id(buf);
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wirename = id(buf);
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addBelInput(belname, id_O, wirename);
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addBelInput(belname, id_I, wirename);
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portname = pairLookup(bel->ports.get(), bel->num_ports, -1, ID_OE)->src_id;
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portname = pairLookup(bel->ports.get(), bel->num_ports, -1, ID_OE)->src_id;
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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wirename = id(buf);
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wirename = id(buf);
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@ -961,12 +961,29 @@ const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
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void Arch::assignArchInfo()
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void Arch::assignArchInfo()
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{
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{
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for (auto &cell : getCtx()->cells) {
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for (auto &cell : getCtx()->cells) {
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IdString cname = cell.first;
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CellInfo *ci = cell.second.get();
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CellInfo *ci = cell.second.get();
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if (ci->type == id("SLICE")) {
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if (ci->type == id("SLICE")) {
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ci->is_slice = true;
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ci->is_slice = true;
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ci->slice_clk = get_net_or_empty(ci, id("CLK"));
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ci->slice_clk = get_net_or_empty(ci, id("CLK"));
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ci->slice_ce = get_net_or_empty(ci, id("CE"));
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ci->slice_ce = get_net_or_empty(ci, id("CE"));
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ci->slice_lsr = get_net_or_empty(ci, id("LSR"));
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ci->slice_lsr = get_net_or_empty(ci, id("LSR"));
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// add timing paths
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addCellTimingClock(cname, id_CLK);
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IdString ports[4] = {id_A, id_B, id_C, id_D};
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for (int i=0; i<4; i++) {
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DelayInfo setup = getDelayFromNS(0.1);
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DelayInfo hold = getDelayFromNS(0.1);
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addCellTimingSetupHold(cname, ports[i], id_CLK, setup, hold);
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}
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DelayInfo clkout = getDelayFromNS(0.1);
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addCellTimingClockToOut(cname, id_Q, id_CLK, clkout);
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for (int i=0; i<4; i++) {
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DelayInfo delay = getDelayFromNS(0.1);
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addCellTimingDelay(cname, ports[i], id_F, delay);
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}
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} else {
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} else {
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ci->is_slice = false;
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ci->is_slice = false;
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}
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}
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@ -97,7 +97,7 @@ struct ArchArgs
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int K = 4;
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int K = 4;
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// y = mx + c relationship between distance and delay for interconnect
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// y = mx + c relationship between distance and delay for interconnect
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// delay estimates
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// delay estimates
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double delayScale = 0.1, delayOffset = 0;
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double delayScale = 0.1, delayOffset = 0.1;
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};
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};
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struct WireInfo;
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struct WireInfo;
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