ice40: Include RAM init data in bitstream
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -77,6 +77,18 @@ int get_param_or_def(const CellInfo *cell, const std::string ¶m,
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return defval;
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return defval;
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}
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}
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std::string get_param_str_or_def(const CellInfo *cell, const std::string ¶m,
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std::string defval = "")
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{
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auto found = cell->params.find(param);
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if (found != cell->params.end())
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return found->second;
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else
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return defval;
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}
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char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
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void write_asc(const Design &design, std::ostream &out)
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void write_asc(const Design &design, std::ostream &out)
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{
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{
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const Chip &chip = design.chip;
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const Chip &chip = design.chip;
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@ -357,6 +369,34 @@ void write_asc(const Design &design, std::ostream &out)
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out << std::endl;
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out << std::endl;
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}
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}
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}
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}
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// Write RAM init data
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for (auto cell : design.cells) {
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if (cell.second->bel != BelId()) {
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if (cell.second->type == "ICESTORM_RAM") {
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const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index];
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int x = beli.x, y = beli.y;
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out << ".ram_data " << x << " " << y << std::endl;
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for (int w = 0; w < 16; w++) {
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std::vector<bool> bits(256);
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std::string init = get_param_str_or_def(
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cell.second,
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std::string("INIT_") + get_hexdigit(w));
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for (int i = 0; i < init.size(); i++) {
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bool val = (init.at((init.size() - 1) - i) == '1');
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bits.at(i) = val;
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}
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for (int i = 0; i < bits.size(); i += 4) {
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int c = bits.at(i) + (bits.at(i + 1) << 1) +
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(bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
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out << get_hexdigit(c);
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}
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out << std::endl;
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}
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out << std::endl;
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}
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}
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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NEXTPNR_NAMESPACE_END
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