Merge pull request #528 from YosysHQ/dave/nexus-lram
nexus: Add basic LRAM support
This commit is contained in:
David Shah
GitHub
commit
ca08add9c9
@ -619,6 +619,10 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
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bb.x0 = std::max<int>(0, bb.x0 - 6);
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bb.x1 = std::min<int>(chip_info->width, bb.x1 + 6);
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}
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if (lram_wires.count(src) || lram_wires.count(dst)) {
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bb.y0 = std::max<int>(0, bb.y0 - 7);
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bb.y1 = std::min<int>(chip_info->width, bb.y1 + 7);
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}
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return bb;
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}
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@ -669,6 +673,13 @@ void Arch::pre_routing()
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dsp_wires.insert(wire);
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}
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}
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if (ci->type == id_LRAM_CORE) {
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for (auto port : sorted_ref(ci->ports)) {
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WireId wire = getBelPinWire(ci->bel, port.first);
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if (wire != WireId())
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lram_wires.insert(wire);
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}
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}
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}
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}
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@ -845,10 +845,12 @@ enum CellPinStyle
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PINSTYLE_LSR = 0x0017, // LSR type signal, invertible and defaults to not reset
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PINSTYLE_DEDI = 0x0000, // dedicated signals, leave alone
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PINSTYLE_PU = 0x4022, // signals that float high and default high
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PINSTYLE_PU_NONCIB = 0x0022, // signals that float high and default high
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PINSTYLE_T = 0x4027, // PIO 'T' signal
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PINSTYLE_ADLSB = 0x4017, // special case of the EBR address MSBs
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PINSTYLE_INV_PD = 0x0017, // invertible, pull down by default
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PINSTYLE_INV_PD_CIB = 0x4017, // invertible, pull down by default
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PINSTYLE_INV_PU = 0x4027, // invertible, pull up by default
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PINSTYLE_IOL_CE = 0x2027, // CE type signal, with explicit 'const-1' config bit
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@ -1363,7 +1365,7 @@ struct Arch : BaseCtx
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// for better DSP bounding boxes
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void pre_routing();
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std::unordered_set<WireId> dsp_wires;
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std::unordered_set<WireId> dsp_wires, lram_wires;
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// -------------------------------------------------
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@ -443,3 +443,24 @@ X(DIVF)
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X(REF_MMD_DIG)
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X(FBK_MMD_DIG)
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X(CLKMUX_FB)
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X(LRAM_CORE)
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X(EBR_SP_EN)
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X(ECC_BYTE_SEL)
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X(CS)
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X(CSA)
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X(CSB)
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X(CSR)
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X(CSW)
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X(OCEA)
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X(OCEB)
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X(RSTR)
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X(DPS)
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X(IGN)
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X(INITN)
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X(STDBYN)
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X(TBISTN)
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X(WE)
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X(CEOUTA)
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X(CEOUTB)
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@ -596,6 +596,44 @@ struct NexusFasmWriter
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}
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pop();
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}
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// Write out config for an LRAM_CORE cell
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void write_lram(const CellInfo *cell)
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{
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BelId bel = cell->bel;
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push_bel(bel);
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write_enum(cell, "ASYNC_RST_RELEASE", "SYNC");
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write_enum(cell, "EBR_SP_EN", "DISABLE");
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write_enum(cell, "ECC_BYTE_SEL", "BYTE_EN");
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write_enum(cell, "GSR", "DISABLED");
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write_enum(cell, "OUT_REGMODE_A", "NO_REG");
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write_enum(cell, "OUT_REGMODE_B", "NO_REG");
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write_enum(cell, "RESETMODE", "SYNC");
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write_enum(cell, "UNALIGNED_READ", "DISABLE");
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write_cell_muxes(cell);
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pop();
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blank();
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Loc l = ctx->getBelLocation(bel);
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push(stringf("IP_LRAM_CORE_R%dC%d", l.y, l.x));
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for (int i = 0; i < 128; i++) {
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IdString param = ctx->id(stringf("INITVAL_%02X", i));
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if (!cell->params.count(param))
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continue;
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auto &prop = cell->params.at(param);
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std::string value;
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if (prop.is_string) {
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NPNR_ASSERT(prop.str.substr(0, 2) == "0x");
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// Lattice-style hex string
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value = prop.str.substr(2);
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value = stringf("5120'h%s", value.c_str());
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} else {
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// True Verilog bitvector
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value = stringf("5120'b%s", prop.str.c_str());
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}
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write_bit(stringf("INITVAL_%02X[5119:0] = %s", i, value.c_str()));
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}
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pop();
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}
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// Write out FASM for unused bels where needed
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void write_unused()
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{
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@ -710,6 +748,8 @@ struct NexusFasmWriter
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write_dsp(ci);
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else if (ci->type == id_PLL_CORE)
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write_pll(ci);
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else if (ci->type == id_LRAM_CORE)
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write_lram(ci);
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blank();
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}
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// Write config for unused bels
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@ -1026,6 +1026,7 @@ struct NexusPacker
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static const std::unordered_map<IdString, IdString> prim_map = {
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{id_OSCA, id_OSC_CORE}, {id_DP16K, id_DP16K_MODE}, {id_PDP16K, id_PDP16K_MODE},
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{id_PDPSC16K, id_PDPSC16K_MODE}, {id_SP16K, id_SP16K_MODE}, {id_FIFO16K, id_FIFO16K_MODE},
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{id_SP512K, id_SP512K_MODE}, {id_DPSC512K, id_DPSC512K_MODE}, {id_PDPSC512K, id_PDPSC512K_MODE},
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{id_PLL, id_PLL_CORE},
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};
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@ -1092,6 +1093,60 @@ struct NexusPacker
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}
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}
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void pack_lram()
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{
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std::unordered_map<IdString, XFormRule> lram_rules;
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lram_rules[id_SP512K_MODE].new_type = id_LRAM_CORE;
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lram_rules[id_SP512K_MODE].set_params.emplace_back(id_EBR_SP_EN, std::string("ENABLE"));
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lram_rules[id_SP512K_MODE].port_xform[id_CE] = id_CEA;
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lram_rules[id_SP512K_MODE].port_xform[id_CS] = id_CSA;
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lram_rules[id_SP512K_MODE].port_xform[id_WE] = id_WEA;
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lram_rules[id_SP512K_MODE].port_xform[id_RSTOUT] = id_RSTA;
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lram_rules[id_SP512K_MODE].port_xform[id_CEOUT] = id_OCEA;
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add_bus_xform(lram_rules[id_SP512K_MODE], "DI", "DIA", 32);
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add_bus_xform(lram_rules[id_SP512K_MODE], "DO", "DOA", 32);
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add_bus_xform(lram_rules[id_SP512K_MODE], "AD", "ADA", 14);
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add_bus_xform(lram_rules[id_SP512K_MODE], "BYTEEN_N", "BENA_N", 4);
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lram_rules[id_PDPSC512K_MODE].new_type = id_LRAM_CORE;
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lram_rules[id_PDPSC512K_MODE].port_xform[id_CEW] = id_CEA;
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lram_rules[id_PDPSC512K_MODE].port_xform[id_CSW] = id_CSA;
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lram_rules[id_PDPSC512K_MODE].port_xform[id_CER] = id_CEB;
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lram_rules[id_PDPSC512K_MODE].port_xform[id_CSR] = id_CSB;
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lram_rules[id_PDPSC512K_MODE].port_xform[id_WE] = id_WEA;
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lram_rules[id_PDPSC512K_MODE].port_xform[id_RSTR] = id_RSTB;
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add_bus_xform(lram_rules[id_PDPSC512K_MODE], "DI", "DIA", 32);
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add_bus_xform(lram_rules[id_PDPSC512K_MODE], "DO", "DOB", 32);
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add_bus_xform(lram_rules[id_PDPSC512K_MODE], "ADW", "ADA", 14);
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add_bus_xform(lram_rules[id_PDPSC512K_MODE], "ADR", "ADB", 14);
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add_bus_xform(lram_rules[id_PDPSC512K_MODE], "BYTEEN_N", "BENA_N", 4);
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lram_rules[id_DPSC512K_MODE].new_type = id_LRAM_CORE;
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lram_rules[id_DPSC512K_MODE].port_xform[id_CEOUTA] = id_OCEA;
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lram_rules[id_DPSC512K_MODE].port_xform[id_CEOUTB] = id_OCEB;
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log_info("Packing LRAM...\n");
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generic_xform(lram_rules, true);
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type != id_LRAM_CORE)
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continue;
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if (str_or_default(ci->params, ctx->id("ECC_BYTE_SEL"), "BYTE_EN") == "BYTE_EN")
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continue;
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for (int i = 0; i < 0x80; i++) {
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// FIXME: document ECC and remove this DRC
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std::string name = stringf("INITVAL_%02X", i);
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if (!ci->params.count(ctx->id(name)))
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continue;
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if (ci->params.at(ctx->id(name)).str.find_last_not_of("0x") == std::string::npos)
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continue;
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log_error("LRAM initialisation is currently unsupported in ECC mode (to disable ECC, set ECC_BYTE_SEL "
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"to BYTE_EN).\n");
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}
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}
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}
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void pack_widefn()
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{
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std::vector<CellInfo *> widefns;
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@ -1883,6 +1938,7 @@ struct NexusPacker
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pack_dsps();
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convert_prims();
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pack_bram();
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pack_lram();
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pack_lutram();
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pack_carries();
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pack_widefn();
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@ -168,7 +168,28 @@ static const std::unordered_map<IdString, Arch::CellPinsData> base_cell_pin_data
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{id_ENEXT, PINSTYLE_DEDI},
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{{}, PINSTYLE_CIB},
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}},
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};
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{id_LRAM_CORE,
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{
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{id_CLK, PINSTYLE_CLK},
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{id_CEA, PINSTYLE_PU_NONCIB},
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{id_CEB, PINSTYLE_PU_NONCIB},
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{id_OCEA, PINSTYLE_PU},
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{id_OCEB, PINSTYLE_PU},
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{id_CSA, PINSTYLE_PU},
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{id_CSB, PINSTYLE_PU},
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{id_RSTA, PINSTYLE_LSR},
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{id_RSTB, PINSTYLE_LSR},
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{id_WEA, PINSTYLE_INV_PD_CIB},
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{id_WEB, PINSTYLE_INV_PD_CIB},
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{id_IGN, PINSTYLE_PU},
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{id_INITN, PINSTYLE_PU},
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{id_STDBYN, PINSTYLE_PU},
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{id_TBISTN, PINSTYLE_PU},
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{id_SCANCLK, PINSTYLE_DEDI},
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{id_SCANRST, PINSTYLE_DEDI},
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{id_OPCGLDCK, PINSTYLE_DEDI},
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{{}, PINSTYLE_CIB},
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}}};
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} // namespace
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void Arch::init_cell_pin_data() { cell_pins_db = base_cell_pin_data; }
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