make source more inline with ecp5
This commit is contained in:
Miodrag Milanovic
myrtle
parent
62ace58204
commit
ca3d32e5ac
209
machxo2/arch.cc
209
machxo2/arch.cc
@ -201,27 +201,6 @@ BelId Arch::getBelByName(IdStringList name) const
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return BelId();
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId ret;
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if (loc.x >= chip_info->width || loc.y >= chip_info->height)
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return BelId();
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ret.location.x = loc.x;
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ret.location.y = loc.y;
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const TileTypePOD *loci = tile_info(ret);
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for (int i = 0; i < loci->bel_data.ssize(); i++) {
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if (loci->bel_data[i].z == loc.z) {
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ret.index = i;
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return ret;
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}
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}
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return BelId();
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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@ -239,24 +218,21 @@ BelRange Arch::getBelsByTile(int x, int y) const
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return br;
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}
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bool Arch::getBelGlobalBuf(BelId bel) const { return false; }
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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WireId ret;
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NPNR_ASSERT(bel != BelId());
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for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires)
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if (bw.port == pin.index) {
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WireId ret;
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ret.location.x = bw.rel_wire_loc.x;
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ret.location.y = bw.rel_wire_loc.y;
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ret.index = bw.wire_index;
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return ret;
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break;
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}
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return WireId();
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return ret;
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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@ -270,35 +246,6 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
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return PORT_INOUT;
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}
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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NPNR_ASSERT(bel != BelId());
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for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) {
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IdString id;
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id.index = bw.port;
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ret.push_back(id);
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}
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return ret;
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}
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// ---------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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for (auto &ppin : package_info->pin_data) {
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if (ppin.name.get() == pin) {
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BelId bel;
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bel.location = ppin.abs_loc;
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bel.index = ppin.bel_index;
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return bel;
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}
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}
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return BelId();
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}
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// ---------------------------------------------------------------
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WireId Arch::getWireByName(IdStringList name) const
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@ -362,6 +309,56 @@ IdStringList Arch::getPipName(PipId pip) const
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// ---------------------------------------------------------------
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BelId Arch::get_package_pin_bel(const std::string &pin) const
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{
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for (auto &ppin : package_info->pin_data) {
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if (ppin.name.get() == pin) {
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BelId bel;
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bel.location = ppin.abs_loc;
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bel.index = ppin.bel_index;
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return bel;
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}
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}
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return BelId();
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}
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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NPNR_ASSERT(bel != BelId());
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for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) {
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IdString id;
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id.index = bw.port;
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ret.push_back(id);
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}
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return ret;
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId ret;
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if (loc.x >= chip_info->width || loc.y >= chip_info->height)
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return BelId();
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ret.location.x = loc.x;
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ret.location.y = loc.y;
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const TileTypePOD *loci = tile_info(ret);
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for (int i = 0; i < loci->bel_data.ssize(); i++) {
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if (loci->bel_data[i].z == loc.z) {
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ret.index = i;
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return ret;
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}
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}
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return BelId();
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}
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// ---------------------------------------------------------------
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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// Taxicab distance multiplied by pipDelay (0.01) and fake wireDelay (0.01).
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@ -370,6 +367,16 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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return (abs(dst.location.x - src.location.x) + abs(dst.location.y - src.location.y)) * (0.01 + 0.01);
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}
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BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
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{
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BoundingBox bb;
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bb.x0 = std::min(src.location.x, dst.location.x);
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bb.y0 = std::min(src.location.y, dst.location.y);
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bb.x1 = std::max(src.location.x, dst.location.x);
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bb.y1 = std::max(src.location.y, dst.location.y);
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return bb;
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}
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delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
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{
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NPNR_UNUSED(src_pin);
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@ -383,16 +390,6 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
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(0.01 + 0.01);
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}
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BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
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{
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BoundingBox bb;
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bb.x0 = std::min(src.location.x, dst.location.x);
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bb.y0 = std::min(src.location.y, dst.location.y);
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bb.x1 = std::max(src.location.x, dst.location.x);
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bb.y1 = std::max(src.location.y, dst.location.y);
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return bb;
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}
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// ---------------------------------------------------------------
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bool Arch::place()
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@ -508,6 +505,16 @@ DecalXY Arch::getPipDecal(PipId pip) const
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return decalxy;
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};
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DecalXY Arch::getGroupDecal(GroupId group) const
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{
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DecalXY decalxy;
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decalxy.decal.type = DecalId::TYPE_GROUP;
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decalxy.decal.location = group.location;
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decalxy.decal.z = group.type;
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decalxy.decal.active = true;
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return decalxy;
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}
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// ---------------------------------------------------------------
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const std::string Arch::defaultPlacer = "heap";
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@ -517,8 +524,6 @@ const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
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const std::string Arch::defaultRouter = "router1";
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const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
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bool Arch::cells_compatible(const CellInfo **cells, int count) const { return false; }
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std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row, int col)
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{
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std::vector<std::pair<std::string, std::string>> ret;
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@ -531,6 +536,72 @@ std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row,
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// -----------------------------------------------------------------------
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GroupId Arch::getGroupByName(IdStringList name) const
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{
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for (auto g : getGroups())
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if (getGroupName(g) == name)
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return g;
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return GroupId();
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}
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IdStringList Arch::getGroupName(GroupId group) const
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{
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std::string suffix;
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switch (group.type) {
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case GroupId::TYPE_SWITCHBOX:
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suffix = "switchbox";
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break;
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default:
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return IdStringList();
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}
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std::array<IdString, 3> ids{x_ids.at(group.location.x), y_ids.at(group.location.y), id(suffix)};
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return IdStringList(ids);
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}
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std::vector<GroupId> Arch::getGroups() const
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{
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std::vector<GroupId> ret;
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for (int y = 1; y < chip_info->height - 1; y++) {
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for (int x = 1; x < chip_info->width - 1; x++) {
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GroupId group;
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group.type = GroupId::TYPE_SWITCHBOX;
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group.location.x = x;
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group.location.y = y;
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ret.push_back(group);
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}
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}
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return ret;
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}
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std::vector<BelId> Arch::getGroupBels(GroupId group) const
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{
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std::vector<BelId> ret;
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return ret;
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}
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std::vector<WireId> Arch::getGroupWires(GroupId group) const
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{
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std::vector<WireId> ret;
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return ret;
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}
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std::vector<PipId> Arch::getGroupPips(GroupId group) const
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{
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std::vector<PipId> ret;
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return ret;
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}
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std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
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{
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std::vector<GroupId> ret;
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return ret;
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}
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// -----------------------------------------------------------------------
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std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
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{
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std::vector<std::pair<IdString, std::string>> ret;
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189
machxo2/arch.h
189
machxo2/arch.h
@ -149,8 +149,6 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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/************************ End of chipdb section. ************************/
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// Iterators
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// Iterate over Bels across tiles.
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struct BelIterator
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{
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const ChipInfoPOD *chip;
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@ -200,7 +198,8 @@ struct BelRange
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BelIterator end() const { return e; }
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};
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// Iterate over Downstream/Upstream Bels for a Wire.
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// -----------------------------------------------------------------------
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struct BelPinIterator
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{
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const BelPortPOD *ptr = nullptr;
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@ -225,7 +224,8 @@ struct BelPinRange
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BelPinIterator end() const { return e; }
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};
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// Iterator over Wires across tiles.
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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const ChipInfoPOD *chip;
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@ -275,7 +275,8 @@ struct WireRange
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WireIterator end() const { return e; }
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};
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// Iterator over Pips across tiles.
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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const ChipInfoPOD *chip;
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@ -325,7 +326,8 @@ struct AllPipRange
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AllPipIterator end() const { return e; }
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};
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// Iterate over Downstream/Upstream Pips for a Wire.
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// -----------------------------------------------------------------------
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struct PipIterator
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{
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@ -383,11 +385,6 @@ struct Arch : BaseArch<ArchRanges>
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mutable dict<IdStringList, PipId> pip_by_name;
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// fast access to X and Y IdStrings for building object names
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std::vector<IdString> x_ids, y_ids;
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// inverse of the above for name->object mapping
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dict<IdString, int> id_to_x, id_to_y;
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enum class LutPermRule
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{
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NONE,
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@ -397,6 +394,9 @@ struct Arch : BaseArch<ArchRanges>
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std::vector<LutPermRule> lutperm_allowed;
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bool disable_router_lutperm = false;
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// For fast, incremental validity checking of split SLICE
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// BEL z-position lookup, x-ored with (index in tile) << 2
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enum LogicBELType
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{
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BEL_COMB = 0,
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@ -427,8 +427,6 @@ struct Arch : BaseArch<ArchRanges>
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~TileStatus() { delete lts; }
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};
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mutable std::vector<TileStatus> tile_status;
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// faster replacements for base_pip2net, base_wire2net
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// indexed by get_pip_vecidx()
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std::vector<NetInfo *> pip2net;
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@ -440,53 +438,49 @@ struct Arch : BaseArch<ArchRanges>
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std::vector<int32_t> pip_tile_vecidx;
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std::vector<int32_t> wire_tile_vecidx;
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// Helpers
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template <typename Id> const TileTypePOD *tile_info(Id &id) const
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{
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return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]);
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}
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// fast access to X and Y IdStrings for building object names
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std::vector<IdString> x_ids, y_ids;
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// inverse of the above for name->object mapping
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dict<IdString, int> id_to_x, id_to_y;
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int get_bel_flat_index(BelId bel) const
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{
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return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
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}
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template <typename Id> inline int tile_index(Id id) const
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{
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return id.location.y * chip_info->width + id.location.x;
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}
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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// General
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ArchArgs args;
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Arch(ArchArgs args);
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static void list_devices();
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std::string getChipName() const override;
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// Extra helper
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std::string get_full_chip_name() const;
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IdString archId() const override { return id_machxo2; }
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ArchArgs archArgs() const override { return args; }
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IdString archArgsToId(ArchArgs args) const override;
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static const int max_loc_bels = 20;
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// -------------------------------------------------
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int getGridDimX() const override { return chip_info->width; }
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int getGridDimY() const override { return chip_info->height; }
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int getTileBelDimZ(int x, int y) const override { return max_loc_bels; }
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static const int max_loc_bels = 32;
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int getGridDimX() const override { return chip_info->width; };
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int getGridDimY() const override { return chip_info->height; };
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int getTileBelDimZ(int, int) const override { return max_loc_bels; };
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// TODO: Make more precise? The CENTER MUX having config bits across
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// tiles can complicate this?
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int getTilePipDimZ(int x, int y) const override { return 2; }
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int getTilePipDimZ(int, int) const override { return 2; };
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char getNameDelimiter() const override { return '/'; }
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// Bels
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// -------------------------------------------------
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BelId getBelByName(IdStringList name) const override;
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template <typename Id> const TileTypePOD *tile_info(Id &id) const
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{
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return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]);
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}
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template <typename Id> inline int tile_index(Id id) const
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{
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return id.location.y * chip_info->width + id.location.x;
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}
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IdStringList getBelName(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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@ -563,7 +557,8 @@ struct Arch : BaseArch<ArchRanges>
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BelId getBelByLocation(Loc loc) const override;
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BelRange getBelsByTile(int x, int y) const override;
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bool getBelGlobalBuf(BelId bel) const override;
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bool getBelGlobalBuf(BelId bel) const override { return false; }
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bool checkBelAvail(BelId bel) const override
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{
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@ -608,13 +603,22 @@ struct Arch : BaseArch<ArchRanges>
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}
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WireId getBelPinWire(BelId bel, IdString pin) const override;
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PortType getBelPinType(BelId bel, IdString pin) const override;
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BelPinRange getWireBelPins(WireId wire) const override
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{
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BelPinRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin();
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range.b.wire_loc = wire.location;
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range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end();
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range.e.wire_loc = wire.location;
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return range;
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}
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std::vector<IdString> getBelPins(BelId bel) const override;
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// Package
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BelId getPackagePinBel(const std::string &pin) const;
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// -------------------------------------------------
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// Wires
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const override
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@ -694,17 +698,6 @@ struct Arch : BaseArch<ArchRanges>
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return range;
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}
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BelPinRange getWireBelPins(WireId wire) const override
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{
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BelPinRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin();
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range.b.wire_loc = wire.location;
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range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end();
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range.e.wire_loc = wire.location;
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return range;
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}
|
||||
|
||||
IdString get_wire_basename(WireId wire) const { return id(tile_info(wire)->wire_data[wire.index].name.get()); }
|
||||
|
||||
WireId get_wire_by_loc_basename(Location loc, std::string basename) const
|
||||
@ -720,7 +713,8 @@ struct Arch : BaseArch<ArchRanges>
|
||||
return WireId();
|
||||
}
|
||||
|
||||
// Pips
|
||||
// -------------------------------------------------
|
||||
|
||||
PipId getPipByName(IdStringList name) const override;
|
||||
IdStringList getPipName(PipId pip) const override;
|
||||
|
||||
@ -809,18 +803,6 @@ struct Arch : BaseArch<ArchRanges>
|
||||
return range;
|
||||
}
|
||||
|
||||
Loc getPipLocation(PipId pip) const override
|
||||
{
|
||||
Loc loc;
|
||||
loc.x = pip.location.x;
|
||||
loc.y = pip.location.y;
|
||||
|
||||
// FIXME: Some Pip's config bits span across tiles. Will Z
|
||||
// be affected by this?
|
||||
loc.z = 0;
|
||||
return loc;
|
||||
}
|
||||
|
||||
WireId getPipSrcWire(PipId pip) const override
|
||||
{
|
||||
WireId wire;
|
||||
@ -863,9 +845,6 @@ struct Arch : BaseArch<ArchRanges>
|
||||
return range;
|
||||
}
|
||||
|
||||
// Extra Pip helpers.
|
||||
int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; }
|
||||
|
||||
std::string get_pip_tilename(PipId pip) const
|
||||
{
|
||||
auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
|
||||
@ -881,32 +860,65 @@ struct Arch : BaseArch<ArchRanges>
|
||||
return chip_info->tiletype_names[tile_info(pip)->pip_data[pip.index].tile_type].get();
|
||||
}
|
||||
|
||||
// Delay
|
||||
Loc getPipLocation(PipId pip) const override
|
||||
{
|
||||
Loc loc;
|
||||
loc.x = pip.location.x;
|
||||
loc.y = pip.location.y;
|
||||
loc.z = 0;
|
||||
return loc;
|
||||
}
|
||||
|
||||
int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; }
|
||||
|
||||
BelId get_package_pin_bel(const std::string &pin) const;
|
||||
//std::string get_bel_package_pin(BelId bel) const;
|
||||
//int get_pio_bel_bank(BelId bel) const;
|
||||
// For getting GCLK, PLL, Vref, etc, pins
|
||||
//std::string get_pio_function_name(BelId bel) const;
|
||||
//BelId get_pio_by_function_name(const std::string &name) const;
|
||||
|
||||
PortType getBelPinType(BelId bel, IdString pin) const override;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
GroupId getGroupByName(IdStringList name) const override;
|
||||
IdStringList getGroupName(GroupId group) const override;
|
||||
std::vector<GroupId> getGroups() const override;
|
||||
std::vector<BelId> getGroupBels(GroupId group) const override;
|
||||
std::vector<WireId> getGroupWires(GroupId group) const override;
|
||||
std::vector<PipId> getGroupPips(GroupId group) const override;
|
||||
std::vector<GroupId> getGroupGroups(GroupId group) const override;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
delay_t estimateDelay(WireId src, WireId dst) const override;
|
||||
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
|
||||
delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
|
||||
delay_t getDelayEpsilon() const override { return 0.001; }
|
||||
delay_t getRipupDelayPenalty() const override { return 0.015; }
|
||||
float getDelayNS(delay_t v) const override { return v; }
|
||||
|
||||
delay_t getDelayFromNS(float ns) const override { return ns; }
|
||||
|
||||
uint32_t getDelayChecksum(delay_t v) const override { return v; }
|
||||
//bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
|
||||
|
||||
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
|
||||
// -------------------------------------------------
|
||||
|
||||
// Flow
|
||||
bool pack() override;
|
||||
bool place() override;
|
||||
bool route() override;
|
||||
|
||||
// Graphics
|
||||
// -------------------------------------------------
|
||||
|
||||
std::vector<GraphicElement> getDecalGraphics(DecalId decal) const override;
|
||||
|
||||
DecalXY getBelDecal(BelId bel) const override;
|
||||
DecalXY getWireDecal(WireId wire) const override;
|
||||
DecalXY getPipDecal(PipId pip) const override;
|
||||
DecalXY getGroupDecal(GroupId group) const override;
|
||||
|
||||
// Placer
|
||||
// -------------------------------------------------
|
||||
// Placement validity checks
|
||||
bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
|
||||
|
||||
// Helper function for above
|
||||
@ -915,15 +927,6 @@ struct Arch : BaseArch<ArchRanges>
|
||||
void assign_arch_info_for_cell(CellInfo *ci);
|
||||
void assignArchInfo() override;
|
||||
|
||||
static const std::string defaultPlacer;
|
||||
static const std::vector<std::string> availablePlacers;
|
||||
static const std::string defaultRouter;
|
||||
static const std::vector<std::string> availableRouters;
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Internal usage
|
||||
bool cells_compatible(const CellInfo **cells, int count) const;
|
||||
|
||||
std::vector<std::pair<std::string, std::string>> get_tiles_at_loc(int row, int col);
|
||||
std::string get_tile_by_type_loc(int row, int col, std::string type) const
|
||||
{
|
||||
@ -956,6 +959,16 @@ struct Arch : BaseArch<ArchRanges>
|
||||
}
|
||||
NPNR_ASSERT_FALSE_STR("no tile with type " + type);
|
||||
}
|
||||
|
||||
static const std::string defaultPlacer;
|
||||
static const std::vector<std::string> availablePlacers;
|
||||
static const std::string defaultRouter;
|
||||
static const std::vector<std::string> availableRouters;
|
||||
|
||||
mutable std::vector<TileStatus> tile_status;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
@ -30,6 +30,8 @@ NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
typedef float delay_t;
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
// https://bugreports.qt.io/browse/QTBUG-80789
|
||||
|
||||
#ifndef Q_MOC_RUN
|
||||
@ -107,6 +109,22 @@ struct PipId
|
||||
unsigned int hash() const { return mkhash(location.hash(), index); }
|
||||
};
|
||||
|
||||
typedef IdString BelBucketId;
|
||||
|
||||
struct GroupId
|
||||
{
|
||||
enum : int8_t
|
||||
{
|
||||
TYPE_NONE,
|
||||
TYPE_SWITCHBOX
|
||||
} type = TYPE_NONE;
|
||||
Location location;
|
||||
|
||||
bool operator==(const GroupId &other) const { return (type == other.type) && (location == other.location); }
|
||||
bool operator!=(const GroupId &other) const { return (type != other.type) || (location != other.location); }
|
||||
unsigned int hash() const { return mkhash(location.hash(), int(type)); }
|
||||
};
|
||||
|
||||
struct DecalId
|
||||
{
|
||||
enum
|
||||
@ -131,14 +149,13 @@ struct DecalId
|
||||
unsigned int hash() const { return mkhash(location.hash(), mkhash(z, int(type))); }
|
||||
};
|
||||
|
||||
typedef IdString GroupId;
|
||||
typedef IdString BelBucketId;
|
||||
typedef IdString ClusterId;
|
||||
|
||||
struct ArchNetInfo
|
||||
{
|
||||
};
|
||||
|
||||
typedef IdString ClusterId;
|
||||
|
||||
struct CellInfo;
|
||||
struct NetInfo;
|
||||
|
||||
struct ArchCellInfo : BaseClusterInfo
|
||||
@ -197,5 +214,4 @@ struct ArchCellInfo : BaseClusterInfo
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif /* MACHXO2_ARCHDEFS_H */
|
||||
|
||||
@ -381,7 +381,7 @@ class Ecp5Packer
|
||||
auto loc_attr = trio->attrs.find(id_LOC);
|
||||
if (loc_attr != trio->attrs.end()) {
|
||||
std::string pin = loc_attr->second.as_string();
|
||||
BelId pinBel = ctx->getPackagePinBel(pin);
|
||||
BelId pinBel = ctx->get_package_pin_bel(pin);
|
||||
if (pinBel == BelId()) {
|
||||
log_error("IO pin '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
|
||||
trio->name.c_str(ctx), pin.c_str(), ctx->package_name);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user