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Wires now encapsulate segments

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This commit is contained in:
Eddie Hung 2018-09-02 16:57:11 -07:00
parent df2f295545
commit ca7eef26ac
3 changed files with 80 additions and 37 deletions
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42
xc7/arch.cc
View File

@ -35,7 +35,7 @@ NEXTPNR_NAMESPACE_BEGIN
std::unique_ptr<const TorcInfo> torc_info;
TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string &inPackageName)
: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_z(construct_bel_to_z(sites, num_bels, site_index_to_type))
: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), segments(ddb->getSegments()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_z(construct_bel_to_z(sites, num_bels, site_index_to_type)), wire_to_tilewire(construct_wire_to_tilewire(segments, tiles)), num_wires(wire_to_tilewire.size())
{
}
std::vector<SiteIndex> TorcInfo::construct_bel_to_site_index(Arch* ctx, const Sites &sites)
@ -102,6 +102,29 @@ std::vector<int8_t> TorcInfo::construct_bel_to_z(const Sites &sites, const int n
}
return bel_to_z;
}
std::vector<Tilewire> TorcInfo::construct_wire_to_tilewire(const Segments& segments, const Tiles& tiles)
{
std::vector<Tilewire> wire_to_tilewire(segments.getCompactSegmentCount());
Tilewire currentTilewire;
for(TileIndex tileIndex(0); tileIndex < tiles.getTileCount(); tileIndex++) {
// iterate over every wire in the tile
const auto& tileInfo = tiles.getTileInfo(tileIndex);
auto tileTypeIndex = tileInfo.getTypeIndex();
auto wireCount = tiles.getWireCount(tileTypeIndex);
currentTilewire.setTileIndex(tileIndex);
for(WireIndex wireIndex(0); wireIndex < wireCount; wireIndex++) {
currentTilewire.setWireIndex(wireIndex);
const auto& currentSegment = segments.getTilewireSegment(currentTilewire);
if (currentSegment.getAnchorTileIndex() != tileIndex) continue;
wire_to_tilewire[currentSegment.getCompactSegmentIndex()] = currentTilewire;
}
}
return wire_to_tilewire;
}
// -----------------------------------------------------------------------
@ -134,7 +157,11 @@ Arch::Arch(ArchArgs args) : args(args)
// if (package_info == nullptr)
// log_error("Unsupported package '%s'.\n", args.package.c_str());
//bel_carry.resize(chip_info->num_bels);
bel_to_cell.resize(torc_info->num_bels);
wire_to_net.resize(torc_info->num_wires);
//pip_to_net.resize(chip_info->num_pips);
//switches_locked.resize(chip_info->num_switches);
}
// -----------------------------------------------------------------------
@ -251,12 +278,13 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
}
}
auto site_index = torc_info->bel_to_site_index[bel.index];
auto &site = torc_info->sites.getSite(site_index);
ret.index = site.getPinTilewire(pin_name);
const auto &site = torc_info->sites.getSite(site_index);
auto &tw = site.getPinTilewire(pin_name);
if (ret.index.isUndefined())
if (tw.isUndefined())
log_error("no wire found for site '%s' pin '%s' \n", torc_info->bel_to_name(bel.index).c_str(), pin_name.c_str());
ret.index = torc_info->tilewire_to_wire(tw);
// NPNR_ASSERT(bel != BelId());
//
@ -592,8 +620,8 @@ DecalXY Arch::getWireDecal(WireId wire) const
{
DecalXY decalxy;
decalxy.decal.type = DecalId::TYPE_WIRE;
//decalxy.decal.index = wire.index;
//decalxy.decal.active = wire_to_net.at(wire.index) != nullptr;
decalxy.decal.index = wire.index;
decalxy.decal.active = wire_to_net.at(wire.index) != nullptr;
return decalxy;
}

69
xc7/arch.h
View File

@ -239,6 +239,7 @@ struct TorcInfo {
std::unique_ptr<const DDB> ddb;
const Sites &sites;
const Tiles &tiles;
const Segments &segments;
const TileInfo& bel_to_tile_info(int32_t index) const {
auto si = bel_to_site_index[index];
@ -249,16 +250,32 @@ struct TorcInfo {
auto si = bel_to_site_index[index];
return sites.getSite(si).getName();
}
std::string wire_to_name(int32_t index) const
{
const auto tw = wire_to_tilewire[index];
ExtendedWireInfo ewi(*ddb, tw);
std::stringstream ss;
ss << ewi.mTileName << "/" << ewi.mWireName;
return ss.str();
}
int32_t tilewire_to_wire(const Tilewire &tw) const
{
const auto& segment = segments.getTilewireSegment(tw);
return segment.getCompactSegmentIndex();
}
const std::vector<SiteIndex> bel_to_site_index;
const int num_bels;
const std::vector<IdString> site_index_to_type;
const std::vector<int8_t> bel_to_z;
const std::vector<Tilewire> wire_to_tilewire;
const int num_wires;
private:
static std::vector<SiteIndex> construct_bel_to_site_index(Arch *ctx, const Sites &sites);
static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites);
static std::vector<int8_t> construct_bel_to_z(const Sites &sites, const int num_bels, const std::vector<IdString> &site_index_to_type);
static std::vector<Tilewire> construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles);
};
extern std::unique_ptr<const TorcInfo> torc_info;
@ -330,11 +347,10 @@ struct BelPinRange
struct WireIterator
{
Tilewire cursor;
int cursor = -1;
// TODO
void operator++() { /*cursor++;*/ }
bool operator!=(const WireIterator &other) const { return !(cursor == other.cursor); }
void operator++() { cursor++; }
bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
WireId operator*() const
{
@ -549,19 +565,18 @@ struct Arch : BaseCtx
IdString getWireName(WireId wire) const
{
NPNR_ASSERT(wire != WireId());
//return id(chip_info->wire_data[wire.index].name.get());
return IdString();
return id(torc_info->wire_to_name(wire.index));
}
IdString getWireType(WireId wire) const;
uint32_t getWireChecksum(WireId wire) const { return hash_value(wire.index); }
uint32_t getWireChecksum(WireId wire) const { return wire.index; }
void bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
{
NPNR_ASSERT(wire != WireId());
//NPNR_ASSERT(wire_to_net[wire.index] == nullptr);
//wire_to_net[wire.index] = net;
NPNR_ASSERT(wire_to_net[wire.index] == nullptr);
wire_to_net[wire.index] = net;
net->wires[wire].pip = PipId();
net->wires[wire].strength = strength;
refreshUiWire(wire);
@ -570,11 +585,11 @@ struct Arch : BaseCtx
void unbindWire(WireId wire)
{
NPNR_ASSERT(wire != WireId());
//NPNR_ASSERT(wire_to_net[wire.index] != nullptr);
NPNR_ASSERT(wire_to_net[wire.index] != nullptr);
//auto &net_wires = wire_to_net[wire.index]->wires;
//auto it = net_wires.find(wire);
//NPNR_ASSERT(it != net_wires.end());
auto &net_wires = wire_to_net[wire.index]->wires;
auto it = net_wires.find(wire);
NPNR_ASSERT(it != net_wires.end());
//auto pip = it->second.pip;
//if (pip != PipId()) {
@ -582,29 +597,29 @@ struct Arch : BaseCtx
// switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
//}
//net_wires.erase(it);
//wire_to_net[wire.index] = nullptr;
net_wires.erase(it);
wire_to_net[wire.index] = nullptr;
refreshUiWire(wire);
}
bool checkWireAvail(WireId wire) const
{
//NPNR_ASSERT(wire != WireId());
//return wire_to_net[wire.index] == nullptr;
NPNR_ASSERT(wire != WireId());
return wire_to_net[wire.index] == nullptr;
return true;
}
NetInfo *getBoundWireNet(WireId wire) const
{
//NPNR_ASSERT(wire != WireId());
//return wire_to_net[wire.index];
NPNR_ASSERT(wire != WireId());
return wire_to_net[wire.index];
return nullptr;
}
NetInfo *getConflictingWireNet(WireId wire) const
{
//NPNR_ASSERT(wire != WireId());
//return wire_to_net[wire.index];
NPNR_ASSERT(wire != WireId());
return wire_to_net[wire.index];
return nullptr;
}
@ -631,8 +646,8 @@ struct Arch : BaseCtx
WireRange getWires() const
{
WireRange range;
//range.b.cursor = 0;
//range.e.cursor = chip_info->num_wires;
range.b.cursor = 0;
range.e.cursor = torc_info->num_wires;
return range;
}
@ -651,8 +666,8 @@ struct Arch : BaseCtx
WireId dst;
//dst.index = chip_info->pip_data[pip.index].dst;
//NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
//wire_to_net[dst.index] = net;
NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
wire_to_net[dst.index] = net;
//net->wires[dst].pip = pip;
//net->wires[dst].strength = strength;
refreshUiPip(pip);
@ -667,8 +682,8 @@ struct Arch : BaseCtx
WireId dst;
//dst.index = chip_info->pip_data[pip.index].dst;
//NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
//wire_to_net[dst.index] = nullptr;
NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
wire_to_net[dst.index] = nullptr;
pip_to_net[pip.index]->wires.erase(dst);
pip_to_net[pip.index] = nullptr;

6
xc7/archdefs.h
View File

@ -74,10 +74,10 @@ struct BelId
struct WireId
{
Tilewire index;
int32_t index = -1;
bool operator==(const WireId &other) const { return index == other.index; }
bool operator!=(const WireId &other) const { return !(index == other.index); }
bool operator!=(const WireId &other) const { return index != other.index; }
};
struct PipId
@ -164,7 +164,7 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
{
return hash_value(wire.index);
return hash<int>()(wire.index);
}
};