diff --git a/generic/arch.cc b/generic/arch.cc
index aca81559..a0123d9e 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -191,6 +191,14 @@ void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pi
 
 void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bels.at(bel).attrs[key] = value; }
 
+void Arch::setLutK(int K) { args.K = K; }
+
+void Arch::setDelayScaling(double scale, double offset)
+{
+    args.delayScale = scale;
+    args.delayOffset = offset;
+}
+
 // ---------------------------------------------------------------
 
 Arch::Arch(ArchArgs args) : chipName("generic"), args(args) {}
@@ -483,10 +491,70 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
     NPNR_ASSERT_FALSE("no clocking info for generic");
 }
 
-bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; }
-bool Arch::isBelLocationValid(BelId bel) const { return true; }
+bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
+{
+    std::vector<const CellInfo *> cells;
+    cells.push_back(cell);
+    Loc loc = getBelLocation(bel);
+    for (auto tbel : getBelsByTile(loc.x, loc.y)) {
+        if (tbel == bel)
+            continue;
+        CellInfo *bound = getBoundBelCell(tbel);
+        if (bound != nullptr)
+            cells.push_back(bound);
+    }
+    return cellsCompatible(cells.data(), int(cells.size()));
+}
+
+bool Arch::isBelLocationValid(BelId bel) const
+{
+    std::vector<const CellInfo *> cells;
+    Loc loc = getBelLocation(bel);
+    for (auto tbel : getBelsByTile(loc.x, loc.y)) {
+        CellInfo *bound = getBoundBelCell(tbel);
+        if (bound != nullptr)
+            cells.push_back(bound);
+    }
+    return cellsCompatible(cells.data(), int(cells.size()));
+}
 
 const std::string Arch::defaultPlacer = "sa";
 const std::vector<std::string> Arch::availablePlacers = {"sa"};
 
+void Arch::assignArchInfo()
+{
+    for (auto &cell : getCtx()->cells) {
+        CellInfo *ci = cell.second.get();
+        if (ci->type == id("GENERIC_SLICE")) {
+            ci->is_slice = true;
+            ci->slice_clk = get_net_or_empty(ci, id("CLK"));
+        } else {
+            ci->is_slice = false;
+        }
+        ci->user_group = int_or_default(ci->attrs, id("PACK_GROUP"), -1);
+    }
+}
+
+bool Arch::cellsCompatible(const CellInfo **cells, int count) const
+{
+    const NetInfo *clk = nullptr;
+    int group = -1;
+    for (int i = 0; i < count; i++) {
+        const CellInfo *ci = cells[i];
+        if (ci->is_slice && ci->slice_clk != nullptr) {
+            if (clk == nullptr)
+                clk = ci->slice_clk;
+            else if (clk != ci->slice_clk)
+                return false;
+        }
+        if (ci->user_group != -1) {
+            if (group == -1)
+                group = ci->user_group;
+            else if (group != ci->user_group)
+                return false;
+        }
+    }
+    return true;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/generic/arch.h b/generic/arch.h
index 5b5d8c55..58e5faa4 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -25,6 +25,11 @@ NEXTPNR_NAMESPACE_BEGIN
 
 struct ArchArgs
 {
+    // Number of LUT inputs
+    int K = 4;
+    // y = mx + c relationship between distance and delay for interconnect
+    // delay estimates
+    double delayScale = 0.1, delayOffset = 0;
 };
 
 struct WireInfo;
@@ -127,6 +132,9 @@ struct Arch : BaseCtx
     void setPipAttr(IdString pip, IdString key, const std::string &value);
     void setBelAttr(IdString bel, IdString key, const std::string &value);
 
+    void setLutK(int K);
+    void setDelayScaling(double scale, double offset);
+
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.
 
@@ -222,7 +230,7 @@ struct Arch : BaseCtx
     uint32_t getDelayChecksum(delay_t v) const { return 0; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
 
-    bool pack() { return true; }
+    bool pack();
     bool place();
     bool route();
 
@@ -243,6 +251,11 @@ struct Arch : BaseCtx
 
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
+
+    // ---------------------------------------------------------------
+    // Internal usage
+    void assignArchInfo();
+    bool cellsCompatible(const CellInfo **cells, int count) const;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/generic/archdefs.h b/generic/archdefs.h
index 2452aa17..978c9c9b 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -55,8 +55,18 @@ typedef IdString DecalId;
 struct ArchNetInfo
 {
 };
+
+struct NetInfo;
+
 struct ArchCellInfo
 {
+    // Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
+    // value may share a tile (-1 = don't care, default if not set)
+    int user_group;
+    // Is a slice type primitive
+    bool is_slice;
+    // Only packing rule for slice type primitives is a single clock per tile
+    const NetInfo *slice_clk;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/generic/cells.cc b/generic/cells.cc
new file mode 100644
index 00000000..14b368b2
--- /dev/null
+++ b/generic/cells.cc
@@ -0,0 +1,139 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "cells.h"
+#include "design_utils.h"
+#include "log.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
+{
+    IdString id = ctx->id(name);
+    NPNR_ASSERT(cell->ports.count(id) == 0);
+    cell->ports[id] = PortInfo{id, nullptr, dir};
+}
+
+std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
+{
+    static int auto_idx = 0;
+    std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
+    if (name.empty()) {
+        new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
+    } else {
+        new_cell->name = ctx->id(name);
+    }
+    new_cell->type = type;
+    if (type == ctx->id("GENERIC_SLICE")) {
+        new_cell->params[ctx->id("K")] = std::to_string(ctx->args.K);
+        new_cell->params[ctx->id("INIT")] = "0";
+        new_cell->params[ctx->id("FF_USED")] = "0";
+
+        for (int i = 0; i < ctx->args.K; i++)
+            add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN);
+
+        add_port(ctx, new_cell.get(), "CLK", PORT_IN);
+
+        add_port(ctx, new_cell.get(), "Q", PORT_OUT);
+    } else if (type == ctx->id("GENERIC_IOB")) {
+        new_cell->params[ctx->id("INPUT_USED")] = "0";
+        new_cell->params[ctx->id("OUTPUT_USED")] = "0";
+        new_cell->params[ctx->id("ENABLE_USED")] = "0";
+
+        add_port(ctx, new_cell.get(), "PAD", PORT_INOUT);
+        add_port(ctx, new_cell.get(), "I", PORT_IN);
+        add_port(ctx, new_cell.get(), "EN", PORT_IN);
+        add_port(ctx, new_cell.get(), "O", PORT_OUT);
+    } else {
+        log_error("unable to create generic cell of type %s", type.c_str(ctx));
+    }
+    return new_cell;
+}
+
+void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
+{
+    lc->params[ctx->id("INIT")] = lut->params[ctx->id("INIT")];
+
+    int lut_k = int_or_default(lut->params, ctx->id("K"), 4);
+    NPNR_ASSERT(lut_k <= ctx->args.K);
+
+    for (int i = 0; i < lut_k; i++) {
+        IdString port = ctx->id("I[" + std::to_string(i) + "]");
+        replace_port(lut, port, lc, port);
+    }
+
+    if (no_dff) {
+        replace_port(lut, ctx->id("Q"), lc, ctx->id("Q"));
+        lc->params[ctx->id("FF_USED")] = "0";
+    }
+}
+
+void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
+{
+    lc->params[ctx->id("FF_USED")] = "1";
+    replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
+
+    if (pass_thru_lut) {
+        lc->params[ctx->id("INIT")] = "2";
+        replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]"));
+    }
+
+    replace_port(dff, ctx->id("Q"), lc, ctx->id("Q"));
+}
+
+void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set<IdString> &todelete_cells)
+{
+    if (nxio->type == ctx->id("$nextpnr_ibuf")) {
+        iob->params[ctx->id("INPUT_USED")] = "1";
+        replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
+    } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
+        iob->params[ctx->id("OUTPUT_USED")] = "1";
+        replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
+    } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
+        // N.B. tristate will be dealt with below
+        iob->params[ctx->id("INPUT_USED")] = "1";
+        iob->params[ctx->id("OUTPUT_USED")] = "1";
+        replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
+        replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
+    } else {
+        NPNR_ASSERT(false);
+    }
+    NetInfo *donet = iob->ports.at(ctx->id("I")).net;
+    CellInfo *tbuf = net_driven_by(
+            ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
+            ctx->id("Y"));
+    if (tbuf) {
+        iob->params[ctx->id("ENABLE_USED")] = "1";
+        replace_port(tbuf, ctx->id("A"), iob, ctx->id("I"));
+        replace_port(tbuf, ctx->id("E"), iob, ctx->id("EN"));
+
+        if (donet->users.size() > 1) {
+            for (auto user : donet->users)
+                log_info("     remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
+            log_error("unsupported tristate IO pattern for IO buffer '%s', "
+                      "instantiate GENERIC_IOB manually to ensure correct behaviour\n",
+                      nxio->name.c_str(ctx));
+        }
+        ctx->nets.erase(donet->name);
+        todelete_cells.insert(tbuf->name);
+    }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/cells.h b/generic/cells.h
new file mode 100644
index 00000000..646d738d
--- /dev/null
+++ b/generic/cells.h
@@ -0,0 +1,55 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2019  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "nextpnr.h"
+
+#ifndef GENERIC_CELLS_H
+#define GENERIC_CELLS_H
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// Create a generic arch cell and return it
+// Name will be automatically assigned if not specified
+std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name = "");
+
+// Return true if a cell is a LUT
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT"); }
+
+// Return true if a cell is a flipflop
+inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("DFF"); }
+
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_SLICE"); }
+
+// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
+// as needed. Set no_dff if a DFF is not being used, so that the output
+// can be reconnected
+void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
+
+// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters
+// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
+// be configured as pass through and D connected to I0, otherwise D will be
+// ignored
+void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
+
+// Convert a nextpnr IO buffer to a GENERIC_IOB
+void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/examples/simple.py b/generic/examples/simple.py
index da41dc5b..17808fc7 100644
--- a/generic/examples/simple.py
+++ b/generic/examples/simple.py
@@ -1,3 +1,16 @@
-ctx.addBel(name="SLICE_X1Y1", type="SLICE_LUT4", loc=Loc(1, 1, 0), gb=False)
-ctx.addBel(name="IO0_I", type="$nextpnr_ibuf", loc=Loc(0, 0, 0), gb=False)
-ctx.addBel(name="IO1_O", type="$nextpnr_obuf", loc=Loc(1, 0, 0), gb=False)
\ No newline at end of file
+X = 12
+Y = 12
+
+def is_io(x, y):
+	return x == 0 or x == X-1 or y == 0 or y == Y-1
+
+
+for x in range(X):
+	for y in range(Y):
+		if is_io(x, y):
+			if x == y:
+				continue
+			for z in range(2):
+				ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
+		else:
+			ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
diff --git a/generic/pack.cc b/generic/pack.cc
new file mode 100644
index 00000000..4d4a76a8
--- /dev/null
+++ b/generic/pack.cc
@@ -0,0 +1,293 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2018-19  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <algorithm>
+#include <iterator>
+#include <unordered_set>
+#include "cells.h"
+#include "design_utils.h"
+#include "log.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// Pack LUTs and LUT-FF pairs
+static void pack_lut_lutffs(Context *ctx)
+{
+    log_info("Packing LUT-FFs..\n");
+
+    std::unordered_set<IdString> packed_cells;
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    for (auto cell : sorted(ctx->cells)) {
+        CellInfo *ci = cell.second;
+        if (ctx->verbose)
+            log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
+        if (is_lut(ctx, ci)) {
+            std::unique_ptr<CellInfo> packed =
+                    create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_LC");
+            std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
+            packed_cells.insert(ci->name);
+            if (ctx->verbose)
+                log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
+            // See if we can pack into a DFF
+            // TODO: LUT cascade
+            NetInfo *o = ci->ports.at(ctx->id("Q")).net;
+            CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true);
+            auto lut_bel = ci->attrs.find(ctx->id("BEL"));
+            bool packed_dff = false;
+            if (dff) {
+                if (ctx->verbose)
+                    log_info("found attached dff %s\n", dff->name.c_str(ctx));
+                auto dff_bel = dff->attrs.find(ctx->id("BEL"));
+                if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
+                    // Locations don't match, can't pack
+                } else {
+                    lut_to_lc(ctx, ci, packed.get(), false);
+                    dff_to_lc(ctx, dff, packed.get(), false);
+                    ctx->nets.erase(o->name);
+                    if (dff_bel != dff->attrs.end())
+                        packed->attrs[ctx->id("BEL")] = dff_bel->second;
+                    packed_cells.insert(dff->name);
+                    if (ctx->verbose)
+                        log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
+                    packed_dff = true;
+                }
+            }
+            if (!packed_dff) {
+                lut_to_lc(ctx, ci, packed.get(), true);
+            }
+            new_cells.push_back(std::move(packed));
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
+
+// Pack FFs not packed as LUTFFs
+static void pack_nonlut_ffs(Context *ctx)
+{
+    log_info("Packing non-LUT FFs..\n");
+
+    std::unordered_set<IdString> packed_cells;
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+
+    for (auto cell : sorted(ctx->cells)) {
+        CellInfo *ci = cell.second;
+        if (is_ff(ctx, ci)) {
+            std::unique_ptr<CellInfo> packed =
+                    create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_DFFLC");
+            std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
+            if (ctx->verbose)
+                log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
+            packed_cells.insert(ci->name);
+            dff_to_lc(ctx, ci, packed.get(), true);
+            new_cells.push_back(std::move(packed));
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
+
+static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value)
+{
+    if (net == nullptr)
+        return false;
+    if (net->name == ctx->id("$PACKER_GND_NET") || net->name == ctx->id("$PACKER_VCC_NET")) {
+        value = (net->name == ctx->id("$PACKER_VCC_NET"));
+        return true;
+    } else {
+        return false;
+    }
+}
+
+// Merge a net into a constant net
+static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
+{
+    orig->driver.cell = nullptr;
+    for (auto user : orig->users) {
+        if (user.cell != nullptr) {
+            CellInfo *uc = user.cell;
+            if (ctx->verbose)
+                log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
+            if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
+                uc->ports[user.port].net = nullptr;
+            } else {
+                uc->ports[user.port].net = constnet;
+                constnet->users.push_back(user);
+            }
+        }
+    }
+    orig->users.clear();
+}
+
+// Pack constants (simple implementation)
+static void pack_constants(Context *ctx)
+{
+    log_info("Packing constants..\n");
+
+    std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND");
+    gnd_cell->params[ctx->id("INIT")] = "0";
+    std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
+    gnd_net->name = ctx->id("$PACKER_GND_NET");
+    gnd_net->driver.cell = gnd_cell.get();
+    gnd_net->driver.port = ctx->id("Q");
+    gnd_cell->ports.at(ctx->id("Q")).net = gnd_net.get();
+
+    std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC");
+    vcc_cell->params[ctx->id("INIT")] = "1";
+    std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
+    vcc_net->name = ctx->id("$PACKER_VCC_NET");
+    vcc_net->driver.cell = vcc_cell.get();
+    vcc_net->driver.port = ctx->id("Q");
+    vcc_cell->ports.at(ctx->id("Q")).net = vcc_net.get();
+
+    std::vector<IdString> dead_nets;
+
+    bool gnd_used = false;
+
+    for (auto net : sorted(ctx->nets)) {
+        NetInfo *ni = net.second;
+        if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+            IdString drv_cell = ni->driver.cell->name;
+            set_net_constant(ctx, ni, gnd_net.get(), false);
+            gnd_used = true;
+            dead_nets.push_back(net.first);
+            ctx->cells.erase(drv_cell);
+        } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+            IdString drv_cell = ni->driver.cell->name;
+            set_net_constant(ctx, ni, vcc_net.get(), true);
+            dead_nets.push_back(net.first);
+            ctx->cells.erase(drv_cell);
+        }
+    }
+
+    if (gnd_used) {
+        ctx->cells[gnd_cell->name] = std::move(gnd_cell);
+        ctx->nets[gnd_net->name] = std::move(gnd_net);
+    }
+    // Vcc cell always inserted for now, as it may be needed during carry legalisation (TODO: trim later if actually
+    // never used?)
+    ctx->cells[vcc_cell->name] = std::move(vcc_cell);
+    ctx->nets[vcc_net->name] = std::move(vcc_net);
+
+    for (auto dn : dead_nets) {
+        ctx->nets.erase(dn);
+    }
+}
+
+static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
+{
+    return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
+           cell->type == ctx->id("$nextpnr_iobuf");
+}
+
+static bool is_generic_iob(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_IOB"); }
+
+// Pack IO buffers
+static void pack_io(Context *ctx)
+{
+    std::unordered_set<IdString> packed_cells;
+    std::unordered_set<IdString> delete_nets;
+
+    std::vector<std::unique_ptr<CellInfo>> new_cells;
+    log_info("Packing IOs..\n");
+
+    for (auto cell : sorted(ctx->cells)) {
+        CellInfo *ci = cell.second;
+        if (is_nextpnr_iob(ctx, ci)) {
+            CellInfo *iob = nullptr;
+            if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
+                iob = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_generic_iob, ctx->id("PAD"), true, ci);
+
+            } else if (ci->type == ctx->id("$nextpnr_obuf")) {
+                NetInfo *net = ci->ports.at(ctx->id("I")).net;
+                iob = net_only_drives(ctx, net, is_generic_iob, ctx->id("PAD"), true, ci);
+            }
+            if (iob != nullptr) {
+                // Trivial case, GENERIC_IOB used. Just destroy the net and the
+                // iobuf
+                log_info("%s feeds GENERIC_IOB %s, removing %s %s.\n", ci->name.c_str(ctx), iob->name.c_str(ctx),
+                         ci->type.c_str(ctx), ci->name.c_str(ctx));
+                NetInfo *net = iob->ports.at(ctx->id("PAD")).net;
+                if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
+                     net->users.size() > 1) ||
+                    (ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr)))
+                    log_error("PAD of %s '%s' connected to more than a single top level IO.\n", iob->type.c_str(ctx),
+                              iob->name.c_str(ctx));
+
+                if (net != nullptr) {
+                    delete_nets.insert(net->name);
+                    iob->ports.at(ctx->id("PAD")).net = nullptr;
+                }
+                if (ci->type == ctx->id("$nextpnr_iobuf")) {
+                    NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
+                    if (net2 != nullptr) {
+                        delete_nets.insert(net2->name);
+                    }
+                }
+            } else {
+                // Create a GENERIC_IOB buffer
+                std::unique_ptr<CellInfo> ice_cell =
+                        create_generic_cell(ctx, ctx->id("GENERIC_IOB"), ci->name.str(ctx) + "$sb_io");
+                nxio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
+                new_cells.push_back(std::move(ice_cell));
+                iob = new_cells.back().get();
+            }
+            packed_cells.insert(ci->name);
+            std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin()));
+        }
+    }
+    for (auto pcell : packed_cells) {
+        ctx->cells.erase(pcell);
+    }
+    for (auto dnet : delete_nets) {
+        ctx->nets.erase(dnet);
+    }
+    for (auto &ncell : new_cells) {
+        ctx->cells[ncell->name] = std::move(ncell);
+    }
+}
+
+// Main pack function
+bool Arch::pack()
+{
+    Context *ctx = getCtx();
+    try {
+        log_break();
+        pack_constants(ctx);
+        pack_io(ctx);
+        pack_lut_lutffs(ctx);
+        pack_nonlut_ffs(ctx);
+        ctx->assignArchInfo();
+        log_info("Checksum: 0x%08x\n", ctx->checksum());
+        return true;
+    } catch (log_execution_error_exception) {
+        return false;
+    }
+}
+
+NEXTPNR_NAMESPACE_END