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Merge pull request #869 from YosysHQ/gatecat/mistral-route-fix

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mistral: DATAIN and DATAOUT of GPIO have swapped
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gatecat 2021-12-12 14:59:34 +00:00 committed by GitHub
commit cb362c2256
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2 changed files with 3 additions and 3 deletions
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2
.github/workflows/mistral_ci.yml vendored
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@ -21,7 +21,7 @@ jobs:
- name: Execute build nextpnr
env:
MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
MISTRAL_REVISION: ecd413421b3b559fc63db13da30275fcd5cd3881
MISTRAL_REVISION: 0edeca112dda9bd463125feb869ddb7511d1acd9
run: |
source ./.github/ci/build_mistral.sh
get_dependencies

4
mistral/io.cc
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@ -31,9 +31,9 @@ void Arch::create_gpio(int x, int y)
BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
// FIXME: is the port index of zero always correct?
add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
bel_data(bel).block_index = z;
}
}