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Remove PLL from attosoc, allow errors in pnr

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This commit is contained in:
Eddie Hung 2018-12-27 23:28:33 -08:00
parent 04757865fe
commit cb6ea8ba84
5 changed files with 26 additions and 16 deletions
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7
xc7/attosoc.pcf
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@ -2,8 +2,7 @@ COMP "led[0]" LOCATE = SITE "M14" LEVEL 1;
COMP "led[1]" LOCATE = SITE "M15" LEVEL 1; COMP "led[1]" LOCATE = SITE "M15" LEVEL 1;
COMP "led[2]" LOCATE = SITE "G14" LEVEL 1; COMP "led[2]" LOCATE = SITE "G14" LEVEL 1;
COMP "led[3]" LOCATE = SITE "D18" LEVEL 1; COMP "led[3]" LOCATE = SITE "D18" LEVEL 1;
COMP "clk" LOCATE = SITE "K17" LEVEL 1; COMP "clki" LOCATE = SITE "K17" LEVEL 1;
COMP "pll.mmcm_adv_inst" LOCATE = SITE "MMCME2_ADV_X1Y2" LEVEL 1;
NET "pll.clkin1" PERIOD = 8 nS ; NET "pll.clkin1" PERIOD = 8 nS ;
#PIN "clk_pin" = BEL "clk.PAD" PINNAME PAD; PIN "clki_pin" = BEL "clki.PAD" PINNAME PAD;
#PIN "clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; PIN "clki_pin" CLOCK_DEDICATED_ROUTE = FALSE;

13
xc7/attosoc.sh
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@ -1,11 +1,14 @@
#!/bin/bash #!/bin/bash
#set -ex set -ex
#rm -f picorv32.v rm -f picorv32.v attosoc.v
#wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
wget https://raw.githubusercontent.com/SymbiFlow/prjtrellis/master/examples/picorv32_versa5g/attosoc.v
yosys attosoc.ys yosys attosoc.ys
../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 150 |& tee attosoc.log set +e
../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 125
set -e
xdl -xdl2ncd attosoc.xdl xdl -xdl2ncd attosoc.xdl
bitgen -w attosoc.ncd -g UnconstrainedPins:Allow #bitgen -w attosoc.ncd -g UnconstrainedPins:Allow
trce attosoc.ncd -v 10 trce attosoc.ncd -v 10
netgen -sim -ofmt vhdl attosoc.ncd -w attosoc_pnr.vhd netgen -sim -ofmt vhdl attosoc.ncd -w attosoc_pnr.vhd

1
xc7/attosoc.ys
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@ -1,7 +1,6 @@
read_verilog attosoc_top.v read_verilog attosoc_top.v
read_verilog attosoc.v read_verilog attosoc.v
read_verilog picorv32.v read_verilog picorv32.v
read_verilog 125MHz_to_60MHz.v
#synth_xilinx -top picorv32 #synth_xilinx -top picorv32

2
xc7/attosoc_tb.vhd
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@ -14,7 +14,7 @@ begin
wait for 4 ns; wait for 4 ns;
end process; end process;
uut: entity work.name port map(clk_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3)); uut: entity work.name port map(clki_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
process process
begin begin

19
xc7/attosoc_top.v
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@ -1,15 +1,24 @@
module top ( module top (
input clk, input clki,
output [3:0] led output [3:0] led
); );
(* keep *) (* keep *)
wire led_unused; wire led_unused;
wire gclk; wire clk;
clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk)); BUFGCTRL clk_gb (
//assign gclk = clk; .I0(clki),
attosoc soc(.clk(gclk), .led({led_unused, led})); .CE0(1'b1),
.CE1(1'b0),
.S0(1'b1),
.S1(1'b0),
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.O(clk)
);
attosoc soc(.clk(clk), .led({led_unused, led}));
endmodule endmodule