Change makefiles to build a FPGA interchange BBA.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
5a7f83c705
commit
cc687b3b72
@ -1,16 +1,16 @@
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NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr)
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NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
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BBA_PATH := $(NEXTPNR_PATH)/build/test.bin
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include ../common.mk
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PACKAGE := csg324
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.PHONY:
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.PHONY: check check_test_data
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check:
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check: check_test_data
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$(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--package $(PACKAGE) \
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--test
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check_test_data:
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$(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--run $(NEXTPNR_PATH)/python/check_arch_api.py
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8
fpga_interchange/examples/common.mk
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8
fpga_interchange/examples/common.mk
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@ -0,0 +1,8 @@
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NEXTPNR_PATH := $(realpath ../../..)
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NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
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BBA_PATH := $(realpath ..)/create_bba/build/test.bin
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RAPIDWRIGHT_PATH := $(realpath ..)/create_bba/build/RapidWright
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INTERCHANGE_PATH := $(realpath ..)/create_bba/build/fpga-interchange-schema/interchange
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DEVICE := $(realpath ..)/create_bba/build/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device
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90
fpga_interchange/examples/create_bba/Makefile
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90
fpga_interchange/examples/create_bba/Makefile
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@ -0,0 +1,90 @@
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#
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# nextpnr -- Next Generation Place and Route
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#
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# Copyright (C) 2021 Symbiflow Authors
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#
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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# This Makefile provides a streamlined way to create an example
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# FPGA interchange BBA suitable for placing and routing on Xilinx A35 parts.
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#
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# FPGA interchange device database is generated via RapidWright.
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#
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# Currently FPGA interchange physical netlist (e.g. place and route route) to
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# FASM support is not done, so bitstream generation relies on RapidWright to
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# convert FPGA interchange logical and physical netlist into a Vivado DCP.
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include ../common.mk
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.DELETE_ON_ERROR:
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.PHONY: all chipdb
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all: chipdb
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build:
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mkdir build
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build/RapidWright: | build
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# FIXME: Update URL / branch as fixes are merged upstream and / or
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# interchange branch on Xilinx/RapidWright is merged to master branch.
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#
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#cd build && git clone -b interchange https://github.com/Xilinx/RapidWright.git
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cd build && git clone -b move_strlist https://github.com/litghost/RapidWright.git
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build/env: | build
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python3 -mvenv build/env
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build/python-fpga-interchange: | build
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cd build && git clone https://github.com/SymbiFlow/python-fpga-interchange.git
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build/fpga-interchange-schema: | build
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cd build && git clone https://github.com/SymbiFlow/fpga-interchange-schema.git
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build/.setup: | build/env build/fpga-interchange-schema build/python-fpga-interchange build/RapidWright
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source build/env/bin/activate && \
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cd build/python-fpga-interchange/ && \
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pip install -r requirements.txt
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touch build/.setup
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$(NEXTPNR_PATH)/build:
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mkdir $(NEXTPNR_PATH)/build
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$(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
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$(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
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make -j -C $(NEXTPNR_PATH)/build
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$(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup
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source build/env/bin/activate && \
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cd build/python-fpga-interchange/ && \
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make \
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-f Makefile.rapidwright \
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NEXTPNR_PATH=$(NEXTPNR_PATH) \
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RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
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INTERCHANGE_PATH=$(INTERCHANGE_PATH)
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$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba
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$(NEXTPNR_PATH)/build/bba/bbasm -l $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba $(BBA_PATH)
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chipdb: $(BBA_PATH)
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test: chipdb
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$(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
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--chipdb $(BBA_PATH) \
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--package csg324 \
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--test
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clean:
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rm -rf build
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@ -1,12 +1,4 @@
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NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr)
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NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
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BBA_PATH := $(NEXTPNR_PATH)/build/test.bin
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RAPIDWRIGHT_PATH := $(shell echo ~/cat_x/RapidWright)
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INTERCHANGE_PATH := $(NEXTPNR_PATH)/3rdparty/fpga-interchange-schema/interchange
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DEVICE := $(shell echo ~/cat_x/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device)
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include ../common.mk
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.DELETE_ON_ERROR:
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.PHONY: all debug clean
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@ -39,7 +31,7 @@ build/$(DESIGN).phys: build/$(DESIGN).netlist
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--xdc $(DESIGN).xdc \
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--netlist build/$(DESIGN).netlist \
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--phys build/$(DESIGN).phys \
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--package $(PACKAGE)
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--package $(PACKAGE) \
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build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
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/usr/bin/time -v python3 -mfpga_interchange.convert \
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@ -64,5 +56,5 @@ build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
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com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \
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build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp
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clean::
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clean:
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rm -rf build
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