Add bypass for CSC mode of GCK
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@ -392,8 +392,8 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
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by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS")
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by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
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# there are CMD signals that can be bypassed as well
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#by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS")
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#by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
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by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS")
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by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
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# Add LUT permutation
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@ -154,7 +154,9 @@ void NgUltraImpl::postRoute()
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case id_WFG.index : wfg_bypass++;
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cell->setParam(ctx->id("type"), Property("WFB"));
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break;
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case id_GCK.index : gck_bypass++; break;
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case id_GCK.index : gck_bypass++;
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cell->setParam(ctx->id("std_mode"), extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
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break;
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default:
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log_error("Unmaped bel type '%s' for routing\n",type.c_str(ctx));
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}
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