From ccda0dc28d9d9713935461b290f4f4fec27e3c5a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 10 May 2024 13:02:58 +0200 Subject: [PATCH] Add bypass for CSC mode of GCK --- himbaechel/uarch/ng-ultra/gen/arch_gen.py | 4 ++-- himbaechel/uarch/ng-ultra/ng_ultra.cc | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/himbaechel/uarch/ng-ultra/gen/arch_gen.py b/himbaechel/uarch/ng-ultra/gen/arch_gen.py index 17f84137..3096fa72 100644 --- a/himbaechel/uarch/ng-ultra/gen/arch_gen.py +++ b/himbaechel/uarch/ng-ultra/gen/arch_gen.py @@ -392,8 +392,8 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes, by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS") by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) # there are CMD signals that can be bypassed as well - #by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS") - #by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) + by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS") + by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0) # Add LUT permutation diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.cc b/himbaechel/uarch/ng-ultra/ng_ultra.cc index adbdf067..ceb931af 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.cc +++ b/himbaechel/uarch/ng-ultra/ng_ultra.cc @@ -154,7 +154,9 @@ void NgUltraImpl::postRoute() case id_WFG.index : wfg_bypass++; cell->setParam(ctx->id("type"), Property("WFB")); break; - case id_GCK.index : gck_bypass++; break; + case id_GCK.index : gck_bypass++; + cell->setParam(ctx->id("std_mode"), extra_data.input == 0 ? Property("BYPASS") : Property("CSC")); + break; default: log_error("Unmaped bel type '%s' for routing\n",type.c_str(ctx)); }