caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add bypass for CSC mode of GCK

Browse Source
This commit is contained in:
Miodrag Milanovic 2024-05-10 13:02:58 +02:00
parent eef97d5e73
commit ccda0dc28d
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
himbaechel/uarch/ng-ultra/gen/arch_gen.py
View File

@ -392,8 +392,8 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS") by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS")
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
# there are CMD signals that can be bypassed as well # there are CMD signals that can be bypassed as well
#by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS") by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS")
#by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
# Add LUT permutation # Add LUT permutation

4
himbaechel/uarch/ng-ultra/ng_ultra.cc
View File

@ -154,7 +154,9 @@ void NgUltraImpl::postRoute()
case id_WFG.index : wfg_bypass++; case id_WFG.index : wfg_bypass++;
cell->setParam(ctx->id("type"), Property("WFB")); cell->setParam(ctx->id("type"), Property("WFB"));
break; break;
case id_GCK.index : gck_bypass++; break; case id_GCK.index : gck_bypass++;
cell->setParam(ctx->id("std_mode"), extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
break;
default: default:
log_error("Unmaped bel type '%s' for routing\n",type.c_str(ctx)); log_error("Unmaped bel type '%s' for routing\n",type.c_str(ctx));
} }