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machxo2: Write out pips to bitstream.

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This commit is contained in:
William D. Jones 2021-01-30 22:42:16 -05:00 committed by gatecat
parent 56656b2b24
commit cf2db7a4c4
3 changed files with 83 additions and 0 deletions
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27
machxo2/arch.cc
View File

@ -124,6 +124,33 @@ std::string Arch::getChipName() const
}
}
std::string Arch::getFullChipName() const
{
std::string name = getChipName();
name += "-";
switch (args.speed) {
case ArchArgs::SPEED_1:
name += "1";
break;
case ArchArgs::SPEED_2:
name += "2";
break;
case ArchArgs::SPEED_3:
name += "3";
case ArchArgs::SPEED_4:
name += "4";
break;
case ArchArgs::SPEED_5:
name += "5";
break;
case ArchArgs::SPEED_6:
name += "6";
break;
}
name += args.package;
return name;
}
IdString Arch::archArgsToId(ArchArgs args) const
{
if (args.type == ArchArgs::LCMXO2_256HC) {

15
machxo2/arch.h
View File

@ -501,6 +501,8 @@ struct Arch : BaseCtx
static bool isAvailable(ArchArgs::ArchArgsTypes chip);
std::string getChipName() const;
// Extra helper
std::string getFullChipName() const;
IdString archId() const { return id("machxo2"); }
ArchArgs archArgs() const { return args; }
@ -882,6 +884,19 @@ struct Arch : BaseCtx
return range;
}
// Extra Pip helpers.
int8_t getPipClass(PipId pip) const { return tileInfo(pip)->pips_data[pip.index].pip_type; }
std::string getPipTilename(PipId pip) const
{
auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
for (int i = 0; i < tileloc.num_tiles; i++) {
if (tileloc.tile_names[i].type_idx == tileInfo(pip)->pips_data[pip.index].tile_type)
return tileloc.tile_names[i].name.get();
}
NPNR_ASSERT_FALSE("failed to find Pip tile");
}
// Group
GroupId getGroupByName(IdString name) const;
IdString getGroupName(GroupId group) const;

41
machxo2/bitstream.cc
View File

@ -22,6 +22,7 @@
#include "bitstream.h"
#include "config.h"
#include "nextpnr.h"
NEXTPNR_NAMESPACE_BEGIN
@ -47,6 +48,35 @@ namespace BaseConfigs {
}
} // namespace BaseConfigs
// Convert an absolute wire name to a relative Trellis one
static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
{
std::string basename = ctx->tileInfo(wire)->wire_data[wire.index].name.get();
std::string prefix2 = basename.substr(0, 2);
if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_")
return basename;
if (loc == wire.location)
return basename;
std::string rel_prefix;
if (wire.location.y < loc.y)
rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
if (wire.location.y > loc.y)
rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
if (wire.location.x > loc.x)
rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
if (wire.location.x < loc.x)
rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
return rel_prefix + "_" + basename;
}
static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
{
std::string tile = ctx->getPipTilename(pip);
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
cc.tiles[tile].add_arc(sink, source);
}
void write_bitstream(Context *ctx, std::string text_config_file)
{
ChipConfig cc;
@ -59,6 +89,17 @@ void write_bitstream(Context *ctx, std::string text_config_file)
NPNR_ASSERT_FALSE("Unsupported device type");
}
cc.metadata.push_back("Part: " + ctx->getFullChipName());
// Add all set, configurable pips to the config
for (auto pip : ctx->getPips()) {
if (ctx->getBoundPipNet(pip) != nullptr) {
if (ctx->getPipClass(pip) == 0) { // ignore fixed pips
set_pip(ctx, cc, pip);
}
}
}
// Configure chip
if (!text_config_file.empty()) {
std::ofstream out_config(text_config_file);