Add constant network test case.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fpga_interchange/examples/const_wire/Makefile

@@ -0,0 +1,8 @@
+DESIGN := wire
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/wire.json: wire.v | build
+	yosys -c run.tcl

fpga_interchange/examples/const_wire/run.tcl

@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog wire.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/wire.json

fpga_interchange/examples/const_wire/wire.v

@@ -0,0 +1,6 @@
+module top(output o, output o2);
+
+assign o = 1'b0;
+assign o2 = 1'b1;
+
+endmodule

fpga_interchange/examples/const_wire/wire.xdc

@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN N15 [get_ports o]
+set_property PACKAGE_PIN N16 [get_ports o2]
+
+set_property IOSTANDARD LVCMOS33 [get_ports o]
+set_property IOSTANDARD LVCMOS33 [get_ports o2]

fpga_interchange/examples/template.mk

@@ -46,6 +46,15 @@ build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
 
 phys_yaml: build/$(DESIGN)_phys.yaml
 
+verbose: build/$(DESIGN).netlist
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE) \
+		--verbose
+
 debug: build/$(DESIGN).netlist
 	gdb --args $(NEXTPNR_BIN) \
 		--chipdb $(BBA_PATH) \