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ice40: Add UltraPlus tiles to database

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-22 16:40:22 +02:00
parent b4764031d9
commit cf78f1b0e4
3 changed files with 86 additions and 4 deletions
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5
ice40/arch.h
View File

@ -166,6 +166,11 @@ enum TileType : uint32_t
TILE_IO = 2,
TILE_RAMB = 3,
TILE_RAMT = 4,
TILE_DSP0 = 5,
TILE_DSP1 = 6,
TILE_DSP2 = 7,
TILE_DSP3 = 8,
TILE_IPCON = 9
};
struct ConfigBitPOD

15
ice40/bitstream.cc
View File

@ -370,6 +370,21 @@ void write_asc(const Context *ctx, std::ostream &out)
case TILE_RAMT:
out << ".ramt_tile";
break;
case TILE_DSP0:
out << ".dsp0_tile";
break;
case TILE_DSP1:
out << ".dsp1_tile";
break;
case TILE_DSP2:
out << ".dsp2_tile";
break;
case TILE_DSP3:
out << ".dsp3_tile";
break;
case TILE_IPCON:
out << ".ipcon_tile";
break;
default:
assert(false);
}

70
ice40/chipdb.py
View File

@ -36,10 +36,6 @@ wire_names = dict()
wire_names_r = dict()
wire_xy = dict()
num_tile_types = 5
tile_sizes = {_: (0, 0) for _ in range(num_tile_types)}
tile_bits = [[] for _ in range(num_tile_types)]
cbit_re = re.compile(r'B(\d+)\[(\d+)\]')
portpins = dict()
@ -69,6 +65,11 @@ tiletypes["LOGIC"] = 1
tiletypes["IO"] = 2
tiletypes["RAMB"] = 3
tiletypes["RAMT"] = 4
tiletypes["DSP0"] = 5
tiletypes["DSP1"] = 6
tiletypes["DSP2"] = 7
tiletypes["DSP3"] = 8
tiletypes["IPCON"] = 9
wiretypes["LOCAL"] = 1
wiretypes["GLOBAL"] = 2
@ -187,6 +188,16 @@ def pipdelay(src, dst):
# print(src, dst, src_type, dst_type, file=sys.stderr)
assert 0
def init_tiletypes(device):
global num_tile_types, tile_sizes, tile_bits
if device == "5k":
num_tile_types = 10
else:
num_tile_types = 5
tile_sizes = {_: (0, 0) for _ in range(num_tile_types)}
tile_bits = [[] for _ in range(num_tile_types)]
with open(sys.argv[1], "r") as f:
mode = None
@ -198,6 +209,7 @@ with open(sys.argv[1], "r") as f:
if line[0] == ".device":
dev_name = line[1]
init_tiletypes(dev_name)
dev_width = int(line[2])
dev_height = int(line[3])
num_wires = int(line[4])
@ -237,6 +249,31 @@ with open(sys.argv[1], "r") as f:
mode = None
continue
if line[0] == ".dsp0_tile":
tiles[(int(line[1]), int(line[2]))] = "dsp0"
mode = None
continue
if line[0] == ".dsp1_tile":
tiles[(int(line[1]), int(line[2]))] = "dsp1"
mode = None
continue
if line[0] == ".dsp2_tile":
tiles[(int(line[1]), int(line[2]))] = "dsp2"
mode = None
continue
if line[0] == ".dsp3_tile":
tiles[(int(line[1]), int(line[2]))] = "dsp3"
mode = None
continue
if line[0] == ".ipcon_tile":
tiles[(int(line[1]), int(line[2]))] = "ipcon"
mode = None
continue
if line[0] == ".logic_tile_bits":
mode = ("bits", 1)
tile_sizes[1] = (int(line[1]), int(line[2]))
@ -257,6 +294,31 @@ with open(sys.argv[1], "r") as f:
tile_sizes[4] = (int(line[1]), int(line[2]))
continue
if line[0] == ".dsp0_tile_bits":
mode = ("bits", 5)
tile_sizes[5] = (int(line[1]), int(line[2]))
continue
if line[0] == ".dsp1_tile_bits":
mode = ("bits", 6)
tile_sizes[6] = (int(line[1]), int(line[2]))
continue
if line[0] == ".dsp2_tile_bits":
mode = ("bits", 7)
tile_sizes[7] = (int(line[1]), int(line[2]))
continue
if line[0] == ".dsp3_tile_bits":
mode = ("bits", 8)
tile_sizes[8] = (int(line[1]), int(line[2]))
continue
if line[0] == ".ipcon_tile_bits":
mode = ("bits", 9)
tile_sizes[9] = (int(line[1]), int(line[2]))
continue
if line[0] == ".ieren":
mode = ("ieren",)
continue