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interchange: fix dedicated interconnect exploration

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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-06-30 18:43:15 +02:00
parent 152c41c3ac
commit cfbd1dfa4d
1 changed files with 14 additions and 8 deletions
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22
fpga_interchange/dedicated_interconnect.cc
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@ -50,7 +50,7 @@ struct WireNode
// //
// Routing networks with depth <= kMaxDepth is considers a dedicated // Routing networks with depth <= kMaxDepth is considers a dedicated
// interconnect. // interconnect.
constexpr int kMaxDepth = 20; constexpr int kMaxDepth = 6;
void DedicatedInterconnect::init(const Context *ctx) void DedicatedInterconnect::init(const Context *ctx)
{ {
@ -115,14 +115,14 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B
WireNode next_node; WireNode next_node;
next_node.wire = wire; next_node.wire = wire;
next_node.depth = node_to_expand.depth += 1; next_node.depth = node_to_expand.depth;
if (next_node.depth > kMaxDepth) { if (node_to_expand.depth > kMaxDepth) {
// Dedicated routing should reach sources by kMaxDepth (with // Dedicated routing should reach sources by kMaxDepth (with
// tuning). // tuning).
// //
// FIXME: Consider removing kMaxDepth and use kMaxSources? // FIXME: Consider removing kMaxDepth and use kMaxSources?
return false; continue;
} }
auto const &wire_data = ctx->wire_info(wire); auto const &wire_data = ctx->wire_info(wire);
@ -162,6 +162,8 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B
} }
} else { } else {
next_node.state = node_to_expand.state; next_node.state = node_to_expand.state;
if (next_node.state == IN_ROUTING)
next_node.depth++;
} }
if (expand_node) { if (expand_node) {
@ -580,9 +582,9 @@ void DedicatedInterconnect::expand_sink_bel(BelId sink_bel, IdString sink_pin, W
WireNode next_node; WireNode next_node;
next_node.wire = wire; next_node.wire = wire;
next_node.depth = node_to_expand.depth += 1; next_node.depth = node_to_expand.depth;
if (next_node.depth > kMaxDepth) { if (node_to_expand.depth > kMaxDepth) {
// Dedicated routing should reach sources by kMaxDepth (with // Dedicated routing should reach sources by kMaxDepth (with
// tuning). // tuning).
// //
@ -625,6 +627,8 @@ void DedicatedInterconnect::expand_sink_bel(BelId sink_bel, IdString sink_pin, W
} }
} else { } else {
next_node.state = node_to_expand.state; next_node.state = node_to_expand.state;
if (next_node.state == IN_ROUTING)
next_node.depth++;
} }
if (expand_node) { if (expand_node) {
@ -723,9 +727,9 @@ void DedicatedInterconnect::expand_source_bel(BelId src_bel, IdString src_pin, W
WireNode next_node; WireNode next_node;
next_node.wire = wire; next_node.wire = wire;
next_node.depth = node_to_expand.depth += 1; next_node.depth = node_to_expand.depth;
if (next_node.depth > kMaxDepth) { if (node_to_expand.depth > kMaxDepth) {
// Dedicated routing should reach sources by kMaxDepth (with // Dedicated routing should reach sources by kMaxDepth (with
// tuning). // tuning).
// //
@ -768,6 +772,8 @@ void DedicatedInterconnect::expand_source_bel(BelId src_bel, IdString src_pin, W
} }
} else { } else {
next_node.state = node_to_expand.state; next_node.state = node_to_expand.state;
if (next_node.state == IN_ROUTING)
next_node.depth++;
} }
if (expand_node) { if (expand_node) {