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ice40: Writing an empty ASC file

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-10 11:56:07 +02:00
parent 89d5280bf6
commit d0431225f1
6 changed files with 141 additions and 1 deletions
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3
.gitignore vendored
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@ -19,3 +19,6 @@ CMakeCache.txt
a.out
*.json
build/
*.asc
*.bin

99
ice40/bitstream.cc Normal file
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@ -0,0 +1,99 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018 David Shah <dave@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "bitstream.h"
#include <vector>
inline TileType tile_at(const Chip &chip, int x, int y)
{
return chip.chip_info.tile_grid[y * chip.chip_info.width + x];
}
void write_asc(const Chip &chip, std::ostream &out)
{
// [y][x][row][col]
const ChipInfoPOD &ci = chip.chip_info;
const BitstreamInfoPOD &bi = *ci.bits_info;
std::vector<std::vector<std::vector<std::vector<int8_t>>>> config;
config.resize(ci.height);
for (int y = 0; y < ci.height; y++) {
config.at(y).resize(ci.width);
for (int x = 0; x < ci.width; x++) {
TileType tile = tile_at(chip, x, y);
int rows = bi.tiles_nonrouting[tile].rows;
int cols = bi.tiles_nonrouting[tile].cols;
config.at(y).at(x).resize(rows, vector<int8_t>(cols));
}
}
out << ".comment from next-pnr" << std::endl;
switch (chip.args.type) {
case ChipArgs::LP384:
out << ".device 384" << std::endl;
break;
case ChipArgs::HX1K:
case ChipArgs::LP1K:
out << ".device 1k" << std::endl;
break;
case ChipArgs::HX8K:
case ChipArgs::LP8K:
out << ".device 8k" << std::endl;
break;
case ChipArgs::UP5K:
out << ".device 5k" << std::endl;
break;
default:
assert(false);
}
// Write config out
for (int y = 0; y < ci.height; y++) {
for (int x = 0; x < ci.width; x++) {
TileType tile = tile_at(chip, x, y);
if (tile == TILE_NONE)
continue;
switch (tile) {
case TILE_LOGIC:
out << ".logic_tile";
break;
case TILE_IO:
out << ".io_tile";
break;
case TILE_RAMB:
out << ".ramb_tile";
break;
case TILE_RAMT:
out << ".ramt_tile";
break;
default:
assert(false);
}
out << " " << x << " " << y << std::endl;
for (auto row : config.at(y).at(x)) {
for (auto col : row) {
if (col == 1)
out << "1";
else
out << "0";
}
out << std::endl;
}
out << std::endl;
}
}
}

28
ice40/bitstream.h Normal file
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@ -0,0 +1,28 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef ICE40_BITSTREAM_H
#define ICE40_BITSTREAM_H
#include <iostream>
#include "chip.h"
void write_asc(const Chip &chip, std::ostream &out);
#endif

2
ice40/chip.cc
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@ -72,7 +72,7 @@ PortPin portPinFromId(IdString id)
// -----------------------------------------------------------------------
Chip::Chip(ChipArgs args)
Chip::Chip(ChipArgs args) : args(args)
{
#ifdef ICE40_HX1K_ONLY
if (args.type == ChipArgs::HX1K) {

1
ice40/chip.h
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@ -407,6 +407,7 @@ struct Chip
Chip(ChipArgs args);
ChipArgs args;
// -------------------------------------------------
BelId getBelByName(IdString name) const;

9
ice40/main.cc
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@ -23,6 +23,7 @@
#include <boost/program_options.hpp>
#include <fstream>
#include <iostream>
#include "bitstream.h"
#include "design.h"
#include "jsonparse.h"
#include "log.h"
@ -69,6 +70,8 @@ int main(int argc, char *argv[])
"python file to execute");
options.add_options()("json", po::value<std::string>(),
"JSON design file to ingest");
options.add_options()("asc", po::value<std::string>(),
"asc bitstream file to write");
options.add_options()("version,v", "show version");
options.add_options()("lp384", "set device type to iCE40LP384");
options.add_options()("lp1k", "set device type to iCE40LP1K");
@ -251,6 +254,12 @@ int main(int argc, char *argv[])
route_design(&design);
}
if (vm.count("asc")) {
std::string filename = vm["asc"].as<std::string>();
std::ofstream f(filename);
write_asc(design.chip, f);
}
if (vm.count("run")) {
std::vector<std::string> files =
vm["run"].as<std::vector<std::string>>();