From d0acb1b2391fb33f0888778a4c644058076343ee Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 28 Jul 2021 12:42:58 +0100
Subject: [PATCH] nexus: Add IOLOGIC pins data

Signed-off-by: gatecat <gatecat@ds0.me>
---
 nexus/arch.h       |  5 +++--
 nexus/constids.inc |  9 +++++++++
 nexus/pins.cc      | 18 ++++++++++++++++++
 3 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/nexus/arch.h b/nexus/arch.h
index 8c330e47..4d2649fd 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -809,8 +809,9 @@ enum CellPinStyle
     PINSTYLE_INV_PD_CIB = 0x4017, // invertible, pull down by default
     PINSTYLE_INV_PU = 0x4027,     // invertible, pull up by default
 
-    PINSTYLE_IOL_CE = 0x2027, // CE type signal, with explicit 'const-1' config bit
-    PINSTYLE_GATE = 0x1011,   // gated signal that defaults to 0
+    PINSTYLE_IOL_CELSR = 0x3007, // CE type signal, with explicit 'const-1' config bit
+    PINSTYLE_IOL_CLK = 0x3107,   // CE type signal, with explicit 'const-1' config bit
+    PINSTYLE_GATE = 0x1011,      // gated signal that defaults to 0
 };
 
 // This represents the mux options for a pin
diff --git a/nexus/constids.inc b/nexus/constids.inc
index d75b6ea5..98817899 100644
--- a/nexus/constids.inc
+++ b/nexus/constids.inc
@@ -505,3 +505,12 @@ X(UED0THEN)
 X(URXCKINE)
 
 X(GENERAL)
+
+X(IOLOGIC)
+X(SIOLOGIC)
+X(LSRIN)
+X(LSROUT)
+X(SCLKIN)
+X(SCLKOUT)
+X(ECLK)
+X(CEIN)
diff --git a/nexus/pins.cc b/nexus/pins.cc
index cef8e72c..e1012755 100644
--- a/nexus/pins.cc
+++ b/nexus/pins.cc
@@ -215,6 +215,24 @@ static const dict<IdString, Arch::CellPinsData> base_cell_pin_data = {
                  {id_U3END3, PINSTYLE_PD_NONCIB},
                  {id_UED0THEN, PINSTYLE_PD_NONCIB},
                  {{}, PINSTYLE_CIB},
+         }},
+        {id_SIOLOGIC,
+         {
+                 {id_SCLKIN, PINSTYLE_IOL_CLK},
+                 {id_SCLKOUT, PINSTYLE_IOL_CLK},
+                 {id_LSRIN, PINSTYLE_IOL_CELSR},
+                 {id_LSROUT, PINSTYLE_IOL_CELSR},
+                 {id_CEIN, PINSTYLE_IOL_CELSR},
+                 {id_CEOUT, PINSTYLE_IOL_CELSR},
+         }},
+        {id_IOLOGIC,
+         {
+                 {id_SCLKIN, PINSTYLE_IOL_CLK},
+                 {id_SCLKOUT, PINSTYLE_IOL_CLK},
+                 {id_LSRIN, PINSTYLE_IOL_CELSR},
+                 {id_LSROUT, PINSTYLE_IOL_CELSR},
+                 {id_CEIN, PINSTYLE_IOL_CELSR},
+                 {id_CEOUT, PINSTYLE_IOL_CELSR},
          }}};
 } // namespace