nexus: Add IOLOGIC pins data

Signed-off-by: gatecat <gatecat@ds0.me>

nexus/arch.h

@@ -809,7 +809,8 @@ enum CellPinStyle
     PINSTYLE_INV_PD_CIB = 0x4017, // invertible, pull down by default
     PINSTYLE_INV_PU = 0x4027,     // invertible, pull up by default
 
-    PINSTYLE_IOL_CE = 0x2027, // CE type signal, with explicit 'const-1' config bit
+    PINSTYLE_IOL_CELSR = 0x3007, // CE type signal, with explicit 'const-1' config bit
+    PINSTYLE_IOL_CLK = 0x3107,   // CE type signal, with explicit 'const-1' config bit
     PINSTYLE_GATE = 0x1011,      // gated signal that defaults to 0
 };
 

nexus/constids.inc

@@ -505,3 +505,12 @@ X(UED0THEN)
 X(URXCKINE)
 
 X(GENERAL)
+
+X(IOLOGIC)
+X(SIOLOGIC)
+X(LSRIN)
+X(LSROUT)
+X(SCLKIN)
+X(SCLKOUT)
+X(ECLK)
+X(CEIN)

nexus/pins.cc

@@ -215,6 +215,24 @@ static const dict<IdString, Arch::CellPinsData> base_cell_pin_data = {
                  {id_U3END3, PINSTYLE_PD_NONCIB},
                  {id_UED0THEN, PINSTYLE_PD_NONCIB},
                  {{}, PINSTYLE_CIB},
+         }},
+        {id_SIOLOGIC,
+         {
+                 {id_SCLKIN, PINSTYLE_IOL_CLK},
+                 {id_SCLKOUT, PINSTYLE_IOL_CLK},
+                 {id_LSRIN, PINSTYLE_IOL_CELSR},
+                 {id_LSROUT, PINSTYLE_IOL_CELSR},
+                 {id_CEIN, PINSTYLE_IOL_CELSR},
+                 {id_CEOUT, PINSTYLE_IOL_CELSR},
+         }},
+        {id_IOLOGIC,
+         {
+                 {id_SCLKIN, PINSTYLE_IOL_CLK},
+                 {id_SCLKOUT, PINSTYLE_IOL_CLK},
+                 {id_LSRIN, PINSTYLE_IOL_CELSR},
+                 {id_LSROUT, PINSTYLE_IOL_CELSR},
+                 {id_CEIN, PINSTYLE_IOL_CELSR},
+                 {id_CEOUT, PINSTYLE_IOL_CELSR},
          }}};
 } // namespace