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nexus: Add IOLOGIC pins data

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-07-28 12:42:58 +01:00
parent 14c676ab49
commit d0acb1b239
3 changed files with 30 additions and 2 deletions
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5
nexus/arch.h
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@ -809,8 +809,9 @@ enum CellPinStyle
PINSTYLE_INV_PD_CIB = 0x4017, // invertible, pull down by default
PINSTYLE_INV_PU = 0x4027, // invertible, pull up by default
PINSTYLE_IOL_CE = 0x2027, // CE type signal, with explicit 'const-1' config bit
PINSTYLE_GATE = 0x1011, // gated signal that defaults to 0
PINSTYLE_IOL_CELSR = 0x3007, // CE type signal, with explicit 'const-1' config bit
PINSTYLE_IOL_CLK = 0x3107, // CE type signal, with explicit 'const-1' config bit
PINSTYLE_GATE = 0x1011, // gated signal that defaults to 0
};
// This represents the mux options for a pin

9
nexus/constids.inc
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@ -505,3 +505,12 @@ X(UED0THEN)
X(URXCKINE)
X(GENERAL)
X(IOLOGIC)
X(SIOLOGIC)
X(LSRIN)
X(LSROUT)
X(SCLKIN)
X(SCLKOUT)
X(ECLK)
X(CEIN)

18
nexus/pins.cc
View File

@ -215,6 +215,24 @@ static const dict<IdString, Arch::CellPinsData> base_cell_pin_data = {
{id_U3END3, PINSTYLE_PD_NONCIB},
{id_UED0THEN, PINSTYLE_PD_NONCIB},
{{}, PINSTYLE_CIB},
}},
{id_SIOLOGIC,
{
{id_SCLKIN, PINSTYLE_IOL_CLK},
{id_SCLKOUT, PINSTYLE_IOL_CLK},
{id_LSRIN, PINSTYLE_IOL_CELSR},
{id_LSROUT, PINSTYLE_IOL_CELSR},
{id_CEIN, PINSTYLE_IOL_CELSR},
{id_CEOUT, PINSTYLE_IOL_CELSR},
}},
{id_IOLOGIC,
{
{id_SCLKIN, PINSTYLE_IOL_CLK},
{id_SCLKOUT, PINSTYLE_IOL_CLK},
{id_LSRIN, PINSTYLE_IOL_CELSR},
{id_LSROUT, PINSTYLE_IOL_CELSR},
{id_CEIN, PINSTYLE_IOL_CELSR},
{id_CEOUT, PINSTYLE_IOL_CELSR},
}}};
} // namespace