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Pack and export DSP

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This commit is contained in:
Miodrag Milanovic 2024-06-18 12:49:20 +02:00
parent d3d3b56b25
commit d14efa1c9b
3 changed files with 28 additions and 1 deletions
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11
himbaechel/uarch/ng-ultra/bitstream.cc
View File

@ -421,6 +421,15 @@ struct BitstreamJsonBackend
close_instance();
}
void write_dsp(CellInfo *cell) {
open_instance(cell);
add_config("raw_config0", extract_bits_or_default(cell->params, ctx->id("raw_config0"), 27));
add_config("raw_config1", extract_bits_or_default(cell->params, ctx->id("raw_config1"), 24));
add_config("raw_config2", extract_bits_or_default(cell->params, ctx->id("raw_config2"), 14));
add_config("raw_config3", extract_bits_or_default(cell->params, ctx->id("raw_config3"), 3));
close_instance();
}
void write_interconnections()
{
for (auto &net : ctx->nets) {
@ -488,7 +497,7 @@ struct BitstreamJsonBackend
//case id_XCDC.index:
//case id_CRX.index:
//case id_CTX.index:
//case id_DSP.index:
case id_DSP.index: write_dsp(cell.second.get()); break;
case id_PLL.index: write_pll(cell.second.get()); break;
//case id_PMA.index:
//case id_Service.index:

17
himbaechel/uarch/ng-ultra/pack.cc
View File

@ -1294,6 +1294,22 @@ void NgUltraPacker::pack_rams(void)
}
}
void NgUltraPacker::pack_dsps(void)
{
log_info("Packing DSPs..\n");
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (!ci.type.in(id_NX_DSP_U))
continue;
ci.type = id_DSP;
bind_attr_loc(&ci, &ci.attrs);
for (auto &p : ci.ports) {
if (p.second.type == PortType::PORT_IN)
disconnect_if_gnd(&ci, p.first);
}
}
}
void NgUltraPacker::setup()
{
// Note: These are per Cell type not Bel type
@ -1381,6 +1397,7 @@ void NgUltraImpl::pack()
packer.pack_plls();
packer.pack_wfgs();
packer.pack_rams();
packer.pack_dsps();
packer.pack_rfs();
packer.pack_cys();
packer.pack_lut_dffs();

1
himbaechel/uarch/ng-ultra/pack.h
View File

@ -51,6 +51,7 @@ struct NgUltraPacker
void pack_rfs();
void pack_rams();
void pack_dsps();
// IO
void pack_iobs();