timing: Debugging implementation of new timing API
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -96,8 +96,8 @@ struct Timing
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net_data.emplace(o->net, TimingData{clkToQ.maxDelay()});
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} else {
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// Also add I/O cells too
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// TODO(eddieh): More generic way of detecting PLLs
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if (portClass == TMG_STARTPOINT || portClass == TMG_IGNORE) { // IGNORE: ????
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// TODO: how to process ignore here
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if (portClass == TMG_STARTPOINT || portClass == TMG_IGNORE) {
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topographical_order.emplace_back(o->net);
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net_data.emplace(o->net, TimingData{});
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}
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@ -138,12 +138,17 @@ struct Timing
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DelayInfo clkToQ;
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for (auto &usr : net->users) {
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IdString clockPort;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
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TimingPortClass usrClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
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if (usrClass == TMG_IGNORE || usrClass == TMG_CLOCK_INPUT)
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continue;
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for (auto &port : usr.cell->ports) {
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if (port.second.type != PORT_OUT || !port.second.net)
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continue;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, port.first, clockPort);
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// Skip if this is a clocked output (but allow non-clocked ones)
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if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE)
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if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT || portClass == TMG_IGNORE ||
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portClass == TMG_GEN_CLOCK)
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continue;
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DelayInfo comb_delay;
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bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
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@ -938,7 +938,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
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} else if (cell->type == id_sb_io) {
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if (port == id("D_IN_0") || port == id("D_IN_1"))
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return TMG_STARTPOINT;
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if (port == id("D_OUT_0") || port == id("D_OUT_1"))
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if (port == id("D_OUT_0") || port == id("D_OUT_1") || port == id("OUTPUT_ENABLE"))
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return TMG_ENDPOINT;
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return TMG_IGNORE;
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} else if (cell->type == id("ICESTORM_PLL")) {
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