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timing: Debugging implementation of new timing API

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-08-08 15:07:41 +02:00
parent 787fe5661c
commit d173ddba36
2 changed files with 10 additions and 5 deletions
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13
common/timing.cc
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@ -96,8 +96,8 @@ struct Timing
net_data.emplace(o->net, TimingData{clkToQ.maxDelay()}); net_data.emplace(o->net, TimingData{clkToQ.maxDelay()});
} else { } else {
// Also add I/O cells too // Also add I/O cells too
// TODO(eddieh): More generic way of detecting PLLs // TODO: how to process ignore here
if (portClass == TMG_STARTPOINT || portClass == TMG_IGNORE) { // IGNORE: ???? if (portClass == TMG_STARTPOINT || portClass == TMG_IGNORE) {
topographical_order.emplace_back(o->net); topographical_order.emplace_back(o->net);
net_data.emplace(o->net, TimingData{}); net_data.emplace(o->net, TimingData{});
} }
@ -138,12 +138,17 @@ struct Timing
DelayInfo clkToQ; DelayInfo clkToQ;
for (auto &usr : net->users) { for (auto &usr : net->users) {
IdString clockPort; IdString clockPort;
TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort); TimingPortClass usrClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
if (usrClass == TMG_IGNORE || usrClass == TMG_CLOCK_INPUT)
continue;
for (auto &port : usr.cell->ports) { for (auto &port : usr.cell->ports) {
if (port.second.type != PORT_OUT || !port.second.net) if (port.second.type != PORT_OUT || !port.second.net)
continue; continue;
TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, port.first, clockPort);
// Skip if this is a clocked output (but allow non-clocked ones) // Skip if this is a clocked output (but allow non-clocked ones)
if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE) if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT || portClass == TMG_IGNORE ||
portClass == TMG_GEN_CLOCK)
continue; continue;
DelayInfo comb_delay; DelayInfo comb_delay;
bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay); bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);

2
ice40/arch.cc
View File

@ -938,7 +938,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
} else if (cell->type == id_sb_io) { } else if (cell->type == id_sb_io) {
if (port == id("D_IN_0") || port == id("D_IN_1")) if (port == id("D_IN_0") || port == id("D_IN_1"))
return TMG_STARTPOINT; return TMG_STARTPOINT;
if (port == id("D_OUT_0") || port == id("D_OUT_1")) if (port == id("D_OUT_0") || port == id("D_OUT_1") || port == id("OUTPUT_ENABLE"))
return TMG_ENDPOINT; return TMG_ENDPOINT;
return TMG_IGNORE; return TMG_IGNORE;
} else if (cell->type == id("ICESTORM_PLL")) { } else if (cell->type == id("ICESTORM_PLL")) {