wip
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@ -384,9 +384,9 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
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pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"MATRIX_PIP")
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pd.extra_data = PipExtraData(ch.strs.id(f"{name}."+inp),PIP_EXTRA_MUX,int(inp[1:])-1,int(out[1:])-1)
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elif (tile_type.startswith("CKG") and bel=="WFG"):
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by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS")
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by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
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#elif (tile_type.startswith("CKG") and bel=="WFG"):
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# by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS")
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# by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
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elif (tile_type.startswith("TUBE") and bel=="GCK"):
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# 20 clock signals comming to 20 GCK, SI1 is bypass
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by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS")
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@ -55,8 +55,23 @@ void NgUltraImpl::init(Context *ctx)
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for (auto bel : ctx->getBels()) {
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if (ctx->getBelType(bel) == id_IOM) {
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std::deque<BelId> wfgs;
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std::deque<BelId> plls;
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IdString bank = tile_name_id(bel.tile);
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iom_bels.emplace(bank,bel);
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WireId belpin = ctx->getBelPinWire(bel,id_CKO1);
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for (auto dh : ctx->getPipsDownhill(belpin)) {
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WireId pip_dst = ctx->getPipDstWire(dh);
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for (const auto &item : ctx->getWireBelPins(pip_dst)) {
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if (boost::contains(ctx->nameOfBel(item.bel),"WFG_C")) {
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wfgs.push_back(item.bel);
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}
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else if (boost::contains(ctx->nameOfBel(item.bel),"PLL")) {
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plls.push_back(item.bel);
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}
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}
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}
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wfg_c_per_bank.emplace(bank,wfgs);
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pll_per_bank.emplace(bank,plls);
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} else if (ctx->getBelType(bel) == id_IOTP) {
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if (ctx->getBelName(bel)[1] == ctx->id("D08P_CLK.IOTP")) {
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global_capable_bels.emplace(bel,id_P17RI);
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@ -72,6 +72,8 @@ public:
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dict<std::string,BelId> locations;
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pool<PipId> blocked_pips;
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dict<IdString, std::deque<BelId>> wfg_c_per_bank;
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dict<IdString, std::deque<BelId>> pll_per_bank;
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private:
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void write_bitstream_json(const std::string &filename);
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@ -1052,6 +1052,15 @@ void NgUltraPacker::insert_ioms()
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ctx->cells.erase(bfr->name);
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}
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}
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!ci.type.in(id_IOM))
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continue;
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insert_wfb(&ci, id_CKO1);
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insert_wfb(&ci, id_CKO2);
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}
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if (bfr_removed)
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log_info(" Removed %d unused BFR\n", bfr_removed);
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}
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@ -1111,14 +1120,22 @@ static int memory_addr_bits(int config,bool ecc)
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void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port)
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{
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NetInfo *net = cell->getPort(port);
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if (net) {
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CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx)));
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cell->disconnectPort(port);
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wfb->connectPort(id_ZO, net);
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NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx)));
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cell->connectPort(port, new_out);
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wfb->connectPort(id_ZI, new_out);
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if (!net) return;
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IdString bank;
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if (cell->type == id_IOM) {
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bank = uarch->tile_name_id(cell->bel.tile);
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log("bank:%s\n",bank.c_str(ctx));
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}
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BelId bel = uarch->wfg_c_per_bank[bank].back();
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uarch->wfg_c_per_bank[bank].pop_back();
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log_info(" Inserting WFB for cell '%s' port '%s'\n", cell->name.c_str(ctx), port.c_str(ctx));
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CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx)));
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cell->disconnectPort(port);
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wfb->connectPort(id_ZO, net);
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NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx)));
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cell->connectPort(port, new_out);
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wfb->connectPort(id_ZI, new_out);
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ctx->bindBel(bel, wfb, PlaceStrength::STRENGTH_LOCKED);
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}
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void NgUltraPacker::constrain_location(CellInfo *cell)
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@ -1497,7 +1514,7 @@ void NgUltraImpl::route_clocks()
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}
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}
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if (dest == WireId()) {
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log_info(" failed to find a route using dedicated resources.\n");
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log_info(" failed to find a route using dedicated resources. %s -> %s\n",glb_net->driver.cell->name.c_str(ctx),usr.cell->name.c_str(ctx));
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}
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while (backtrace.count(dest)) {
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auto uh = backtrace[dest];
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