From d19702d1a8174e64eb47c6adf4293f24a854b08e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 18 Jun 2024 17:12:18 +0200 Subject: [PATCH] wip --- himbaechel/uarch/ng-ultra/gen/arch_gen.py | 6 ++--- himbaechel/uarch/ng-ultra/ng_ultra.cc | 15 +++++++++++ himbaechel/uarch/ng-ultra/ng_ultra.h | 2 ++ himbaechel/uarch/ng-ultra/pack.cc | 33 +++++++++++++++++------ 4 files changed, 45 insertions(+), 11 deletions(-) diff --git a/himbaechel/uarch/ng-ultra/gen/arch_gen.py b/himbaechel/uarch/ng-ultra/gen/arch_gen.py index 70c53207..a5384d5e 100644 --- a/himbaechel/uarch/ng-ultra/gen/arch_gen.py +++ b/himbaechel/uarch/ng-ultra/gen/arch_gen.py @@ -384,9 +384,9 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes, pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"MATRIX_PIP") pd.extra_data = PipExtraData(ch.strs.id(f"{name}."+inp),PIP_EXTRA_MUX,int(inp[1:])-1,int(out[1:])-1) - elif (tile_type.startswith("CKG") and bel=="WFG"): - by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS") - by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) + #elif (tile_type.startswith("CKG") and bel=="WFG"): + # by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS") + # by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) elif (tile_type.startswith("TUBE") and bel=="GCK"): # 20 clock signals comming to 20 GCK, SI1 is bypass by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS") diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.cc b/himbaechel/uarch/ng-ultra/ng_ultra.cc index dcf4e8b3..7c9edf2c 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.cc +++ b/himbaechel/uarch/ng-ultra/ng_ultra.cc @@ -55,8 +55,23 @@ void NgUltraImpl::init(Context *ctx) for (auto bel : ctx->getBels()) { if (ctx->getBelType(bel) == id_IOM) { std::deque wfgs; + std::deque plls; IdString bank = tile_name_id(bel.tile); iom_bels.emplace(bank,bel); + WireId belpin = ctx->getBelPinWire(bel,id_CKO1); + for (auto dh : ctx->getPipsDownhill(belpin)) { + WireId pip_dst = ctx->getPipDstWire(dh); + for (const auto &item : ctx->getWireBelPins(pip_dst)) { + if (boost::contains(ctx->nameOfBel(item.bel),"WFG_C")) { + wfgs.push_back(item.bel); + } + else if (boost::contains(ctx->nameOfBel(item.bel),"PLL")) { + plls.push_back(item.bel); + } + } + } + wfg_c_per_bank.emplace(bank,wfgs); + pll_per_bank.emplace(bank,plls); } else if (ctx->getBelType(bel) == id_IOTP) { if (ctx->getBelName(bel)[1] == ctx->id("D08P_CLK.IOTP")) { global_capable_bels.emplace(bel,id_P17RI); diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.h b/himbaechel/uarch/ng-ultra/ng_ultra.h index 80e98270..4e8e7e9a 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.h +++ b/himbaechel/uarch/ng-ultra/ng_ultra.h @@ -72,6 +72,8 @@ public: dict locations; pool blocked_pips; + dict> wfg_c_per_bank; + dict> pll_per_bank; private: void write_bitstream_json(const std::string &filename); diff --git a/himbaechel/uarch/ng-ultra/pack.cc b/himbaechel/uarch/ng-ultra/pack.cc index c8ed1fdf..3403ddba 100644 --- a/himbaechel/uarch/ng-ultra/pack.cc +++ b/himbaechel/uarch/ng-ultra/pack.cc @@ -1052,6 +1052,15 @@ void NgUltraPacker::insert_ioms() ctx->cells.erase(bfr->name); } } + + for (auto &cell : ctx->cells) { + CellInfo &ci = *cell.second; + if (!ci.type.in(id_IOM)) + continue; + insert_wfb(&ci, id_CKO1); + insert_wfb(&ci, id_CKO2); + } + if (bfr_removed) log_info(" Removed %d unused BFR\n", bfr_removed); } @@ -1111,14 +1120,22 @@ static int memory_addr_bits(int config,bool ecc) void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port) { NetInfo *net = cell->getPort(port); - if (net) { - CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx))); - cell->disconnectPort(port); - wfb->connectPort(id_ZO, net); - NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx))); - cell->connectPort(port, new_out); - wfb->connectPort(id_ZI, new_out); + if (!net) return; + IdString bank; + if (cell->type == id_IOM) { + bank = uarch->tile_name_id(cell->bel.tile); + log("bank:%s\n",bank.c_str(ctx)); } + BelId bel = uarch->wfg_c_per_bank[bank].back(); + uarch->wfg_c_per_bank[bank].pop_back(); + log_info(" Inserting WFB for cell '%s' port '%s'\n", cell->name.c_str(ctx), port.c_str(ctx)); + CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx))); + cell->disconnectPort(port); + wfb->connectPort(id_ZO, net); + NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx))); + cell->connectPort(port, new_out); + wfb->connectPort(id_ZI, new_out); + ctx->bindBel(bel, wfb, PlaceStrength::STRENGTH_LOCKED); } void NgUltraPacker::constrain_location(CellInfo *cell) @@ -1497,7 +1514,7 @@ void NgUltraImpl::route_clocks() } } if (dest == WireId()) { - log_info(" failed to find a route using dedicated resources.\n"); + log_info(" failed to find a route using dedicated resources. %s -> %s\n",glb_net->driver.cell->name.c_str(ctx),usr.cell->name.c_str(ctx)); } while (backtrace.count(dest)) { auto uh = backtrace[dest];