caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

wip

Browse Source
This commit is contained in:
Miodrag Milanovic 2024-06-18 17:12:18 +02:00
parent d14efa1c9b
commit d19702d1a8
4 changed files with 45 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
himbaechel/uarch/ng-ultra/gen/arch_gen.py
View File

@ -384,9 +384,9 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"MATRIX_PIP") pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"MATRIX_PIP")
pd.extra_data = PipExtraData(ch.strs.id(f"{name}."+inp),PIP_EXTRA_MUX,int(inp[1:])-1,int(out[1:])-1) pd.extra_data = PipExtraData(ch.strs.id(f"{name}."+inp),PIP_EXTRA_MUX,int(inp[1:])-1,int(out[1:])-1)
elif (tile_type.startswith("CKG") and bel=="WFG"): #elif (tile_type.startswith("CKG") and bel=="WFG"):
by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS") # by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS")
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0) # by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
elif (tile_type.startswith("TUBE") and bel=="GCK"): elif (tile_type.startswith("TUBE") and bel=="GCK"):
# 20 clock signals comming to 20 GCK, SI1 is bypass # 20 clock signals comming to 20 GCK, SI1 is bypass
by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS") by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS")

15
himbaechel/uarch/ng-ultra/ng_ultra.cc
View File

@ -55,8 +55,23 @@ void NgUltraImpl::init(Context *ctx)
for (auto bel : ctx->getBels()) { for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) == id_IOM) { if (ctx->getBelType(bel) == id_IOM) {
std::deque<BelId> wfgs; std::deque<BelId> wfgs;
std::deque<BelId> plls;
IdString bank = tile_name_id(bel.tile); IdString bank = tile_name_id(bel.tile);
iom_bels.emplace(bank,bel); iom_bels.emplace(bank,bel);
WireId belpin = ctx->getBelPinWire(bel,id_CKO1);
for (auto dh : ctx->getPipsDownhill(belpin)) {
WireId pip_dst = ctx->getPipDstWire(dh);
for (const auto &item : ctx->getWireBelPins(pip_dst)) {
if (boost::contains(ctx->nameOfBel(item.bel),"WFG_C")) {
wfgs.push_back(item.bel);
}
else if (boost::contains(ctx->nameOfBel(item.bel),"PLL")) {
plls.push_back(item.bel);
}
}
}
wfg_c_per_bank.emplace(bank,wfgs);
pll_per_bank.emplace(bank,plls);
} else if (ctx->getBelType(bel) == id_IOTP) { } else if (ctx->getBelType(bel) == id_IOTP) {
if (ctx->getBelName(bel)[1] == ctx->id("D08P_CLK.IOTP")) { if (ctx->getBelName(bel)[1] == ctx->id("D08P_CLK.IOTP")) {
global_capable_bels.emplace(bel,id_P17RI); global_capable_bels.emplace(bel,id_P17RI);

2
himbaechel/uarch/ng-ultra/ng_ultra.h
View File

@ -72,6 +72,8 @@ public:
dict<std::string,BelId> locations; dict<std::string,BelId> locations;
pool<PipId> blocked_pips; pool<PipId> blocked_pips;
dict<IdString, std::deque<BelId>> wfg_c_per_bank;
dict<IdString, std::deque<BelId>> pll_per_bank;
private: private:
void write_bitstream_json(const std::string &filename); void write_bitstream_json(const std::string &filename);

23
himbaechel/uarch/ng-ultra/pack.cc
View File

@ -1052,6 +1052,15 @@ void NgUltraPacker::insert_ioms()
ctx->cells.erase(bfr->name); ctx->cells.erase(bfr->name);
} }
} }
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (!ci.type.in(id_IOM))
continue;
insert_wfb(&ci, id_CKO1);
insert_wfb(&ci, id_CKO2);
}
if (bfr_removed) if (bfr_removed)
log_info(" Removed %d unused BFR\n", bfr_removed); log_info(" Removed %d unused BFR\n", bfr_removed);
} }
@ -1111,14 +1120,22 @@ static int memory_addr_bits(int config,bool ecc)
void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port) void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port)
{ {
NetInfo *net = cell->getPort(port); NetInfo *net = cell->getPort(port);
if (net) { if (!net) return;
IdString bank;
if (cell->type == id_IOM) {
bank = uarch->tile_name_id(cell->bel.tile);
log("bank:%s\n",bank.c_str(ctx));
}
BelId bel = uarch->wfg_c_per_bank[bank].back();
uarch->wfg_c_per_bank[bank].pop_back();
log_info(" Inserting WFB for cell '%s' port '%s'\n", cell->name.c_str(ctx), port.c_str(ctx));
CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx))); CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx)));
cell->disconnectPort(port); cell->disconnectPort(port);
wfb->connectPort(id_ZO, net); wfb->connectPort(id_ZO, net);
NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx))); NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx)));
cell->connectPort(port, new_out); cell->connectPort(port, new_out);
wfb->connectPort(id_ZI, new_out); wfb->connectPort(id_ZI, new_out);
} ctx->bindBel(bel, wfb, PlaceStrength::STRENGTH_LOCKED);
} }
void NgUltraPacker::constrain_location(CellInfo *cell) void NgUltraPacker::constrain_location(CellInfo *cell)
@ -1497,7 +1514,7 @@ void NgUltraImpl::route_clocks()
} }
} }
if (dest == WireId()) { if (dest == WireId()) {
log_info(" failed to find a route using dedicated resources.\n"); log_info(" failed to find a route using dedicated resources. %s -> %s\n",glb_net->driver.cell->name.c_str(ctx),usr.cell->name.c_str(ctx));
} }
while (backtrace.count(dest)) { while (backtrace.count(dest)) {
auto uh = backtrace[dest]; auto uh = backtrace[dest];