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Add relative constraints to position MULT18X18D near connected ALU54B.

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This commit is contained in:
Adam Greig 2021-03-31 02:20:09 +01:00
parent 9538954cc6
commit d4c688297c
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GPG Key ID: 8B3FE5477B1DD9A0
2 changed files with 29 additions and 0 deletions
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5
ecp5/arch.cc
View File

@ -574,6 +574,11 @@ bool Arch::place()
PlacerHeapCfg cfg(getCtx());
cfg.criticalityExponent = 4;
cfg.ioBufTypes.insert(id_TRELLIS_IO);
cfg.cellGroups.emplace_back();
cfg.cellGroups.back().insert(id_MULT18X18D);
cfg.cellGroups.back().insert(id_ALU54B);
if (!placer_heap(getCtx(), cfg))
return false;
} else if (placer == "sa") {

24
ecp5/pack.cc
View File

@ -1573,6 +1573,30 @@ class Ecp5Packer
autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
for (int i = 0; i < 11; i++)
autocreate_empty_port(ci, ctx->id("OP" + std::to_string(i)));
// Find the MULT18X18Ds feeding this ALU54B's inputs and
// constrain them to the ALU.
for (auto port : {id_MA0, id_MB0}) {
CellInfo *mult = net_driven_by(
ctx, ci->ports.at(port).net,
[](const Context *ctx, const CellInfo *cell) {
return cell->type == id_MULT18X18D;
}, id_P0
);
if(mult != nullptr) {
if(port == id_MA0) {
mult->constr_x = mult->constr_z = -3;
} else if(port == id_MB0) {
mult->constr_x = mult->constr_z = -2;
}
mult->constr_y = 0;
mult->constr_parent = ci;
ci->constr_children.push_back(mult);
log_info("DSP: Constraining MULT18X18D '%s' to ALU54B '%s' port %s\n",
mult->name.c_str(ctx), cell.first.c_str(ctx),
ctx->nameOf(port));
}
}
}
}
}