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Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-pol

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ice40: Fix UltraPlus BRAM clock polarity
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myrtle 2022-09-16 06:38:04 +02:00 committed by GitHub
commit d58e85f297
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 3 deletions
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10
ice40/bitstream.cc
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@ -620,9 +620,13 @@ void write_asc(const Context *ctx, std::ostream &out)
bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W);
int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE);
int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE);
set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) {
set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r);
set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w);
} else {
set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
}
set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1);
set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2);
set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1);