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Fix chipdb UltraPlus wires

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-20 13:10:40 +02:00
parent c667f640d5
commit d5a032d00e
1 changed files with 1 additions and 1 deletions
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2
ice40/chipdb.py
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@ -124,7 +124,7 @@ def wire_type(name):
wt = "LOCAL"
elif name in ("OUT_ENB", "cen", "inclk", "latch", "outclk", "clk", "s_r", "carry_in", "carry_in_mux"):
wt = "LOCAL"
elif name in ("in_0", "in_1", "in_2", "in_3", "cout", "lout", "out", "fabout"):
elif name in ("in_0", "in_1", "in_2", "in_3", "cout", "lout", "out", "fabout") or name.startswith("slf_op") or name.startswith("O_"):
wt = "LOCAL"
elif name.startswith("local_g") or name.startswith("glb2local_"):
wt = "LOCAL"