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Added fallback to VCC as the preferred constant if the architecture does not specify one.

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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2022-05-12 11:55:16 +02:00
parent 7c7a4f0959
commit d75c45c63f
3 changed files with 20 additions and 6 deletions
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13
fpga_interchange/arch.cc
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@ -301,6 +301,12 @@ void Arch::init()
for (size_t tile_type = 0; tile_type < chip_info->tile_types.size(); ++tile_type) { for (size_t tile_type = 0; tile_type < chip_info->tile_types.size(); ++tile_type) {
pseudo_pip_data.init_tile_type(getCtx(), tile_type); pseudo_pip_data.init_tile_type(getCtx(), tile_type);
} }
// Warn if there is no preferred constant net defined in the architecture
IdString const_net_name(getCtx()->chip_info->constants->best_constant_net);
if (const_net_name == IdString()) {
log_warning("The architecture does not specify preferred constant net. Using VCC as default.\n");
}
} }
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
@ -877,7 +883,12 @@ static void prepare_sites_for_routing(Context *ctx)
IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name); IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
IdString const_net_name(ctx->chip_info->constants->best_constant_net); IdString const_net_name(ctx->chip_info->constants->best_constant_net);
NPNR_ASSERT(const_net_name == vcc_net_name || const_net_name == gnd_net_name); NPNR_ASSERT(const_net_name == IdString() || const_net_name == vcc_net_name || const_net_name == gnd_net_name);
// FIXME: Use VCC if the architecture does not device the best constant
if (const_net_name == IdString()) {
const_net_name = vcc_net_name;
}
for (BelId bel : ctx->getBels()) { for (BelId bel : ctx->getBels()) {
CellInfo *cell = ctx->getBoundBelCell(bel); CellInfo *cell = ctx->getBoundBelCell(bel);

6
fpga_interchange/luts.cc
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@ -429,8 +429,7 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
if ((used_pins & (1 << bel_pin_idx)) == 0) { if ((used_pins & (1 << bel_pin_idx)) == 0) {
NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1); NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Const); cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Const);
} } else {
else {
cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal); cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
} }
} }
@ -442,8 +441,7 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping
NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1); NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
auto pin = lutBel.pins.at(bel_pin_idx); auto pin = lutBel.pins.at(bel_pin_idx);
cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Const); cell.lutCell.pin_connections.emplace(pin, LutCell::PinConnection::Const);
} } else {
else {
cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal); cell.lutCell.pin_connections.emplace(lutBel.pins.at(bel_pin_idx), LutCell::PinConnection::Signal);
} }
} }

7
fpga_interchange/site_arch.cc
View File

@ -140,7 +140,12 @@ SiteArch::SiteArch(const SiteInformation *site_info)
IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name); IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name);
IdString const_net_name(ctx->chip_info->constants->best_constant_net); IdString const_net_name(ctx->chip_info->constants->best_constant_net);
NPNR_ASSERT(const_net_name == vcc_net_name || const_net_name == gnd_net_name); NPNR_ASSERT(const_net_name == IdString() || const_net_name == vcc_net_name || const_net_name == gnd_net_name);
// FIXME: Use VCC if the architecture does not device the best constant
if (const_net_name == IdString()) {
const_net_name = vcc_net_name;
}
for (CellInfo *cell : site_info->cells_in_site) { for (CellInfo *cell : site_info->cells_in_site) {
for (const auto &pin_pair : cell->cell_bel_pins) { for (const auto &pin_pair : cell->cell_bel_pins) {