fpga_intrchange: add cmake infrastructure to generate chipdbs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
701587241f
commit
d77d0ff34a
112
fpga_interchange/examples/chipdb.cmake
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112
fpga_interchange/examples/chipdb.cmake
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@ -0,0 +1,112 @@
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function(create_rapidwright_device_db)
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set(options)
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set(oneValueArgs part)
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set(multiValueArgs)
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cmake_parse_arguments(
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create_rapidwright_device_db
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"${options}"
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"${oneValueArgs}"
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"${multiValueArgs}"
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${ARGN}
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)
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set(part ${create_rapidwright_device_db_part})
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set(rapidwright_device_db ${CMAKE_CURRENT_BINARY_DIR}/${part}.device)
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add_custom_command(
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OUTPUT ${rapidwright_device_db}
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COMMAND
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RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
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${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh
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com.xilinx.rapidwright.interchange.DeviceResourcesExample
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${part}
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DEPENDS
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${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh
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)
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add_custom_target(rapidwright-${part}-device DEPENDS ${rapidwright_device_db})
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set_property(TARGET rapidwright-${part}-device PROPERTY LOCATION ${rapidwright_device_db})
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endfunction()
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function(generate_chipdb)
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set(options)
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set(oneValueArgs part)
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set(multiValueArgs)
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cmake_parse_arguments(
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generate_chipdb
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"${options}"
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"${oneValueArgs}"
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"${multiValueArgs}"
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${ARGN}
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)
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set(part ${generate_chipdb_part})
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create_rapidwright_device_db(part ${part})
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set(rapidwright_device_target rapidwright-${part}-device)
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get_property(rapidwright_device_loc TARGET ${rapidwright_device_target} PROPERTY LOCATION)
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set(constraints_device ${CMAKE_CURRENT_BINARY_DIR}/${part}_constraints.device)
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add_custom_command(
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OUTPUT ${constraints_device}
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COMMAND
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python3 -mfpga_interchange.patch
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--schema device
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--patch_path constraints
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--patch_format yaml
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${rapidwright_device_loc}
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${PYTHON_INTERCHANGE_PATH}/test_data/series7_constraints.yaml
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${constraints_device}
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DEPENDS
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${rapidwright_device_target}
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)
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add_custom_target(constraints-${part}-device DEPENDS ${constraints_device})
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set(constraints_luts_device ${CMAKE_CURRENT_BINARY_DIR}/${part}_constraints_luts.device)
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add_custom_command(
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OUTPUT ${constraints_luts_device}
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COMMAND
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python3 -mfpga_interchange.patch
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--schema device
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--patch_path lutDefinitions
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--patch_format yaml
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${constraints_device}
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${PYTHON_INTERCHANGE_PATH}/test_data/series7_luts.yaml
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${constraints_luts_device}
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DEPENDS
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${constraints_device}
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)
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add_custom_target(constraints-luts-${part}-device DEPENDS ${constraints_luts_device})
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set_property(TARGET constraints-luts-${part}-device PROPERTY LOCATION ${constraints_luts_device})
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set(chipdb_bba ${chipdb_dir}/chipdb-${part}.bba)
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add_custom_command(
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OUTPUT ${chipdb_bba}
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COMMAND
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python3 -mfpga_interchange.nextpnr_emit
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--output_dir ${chipdb_dir}
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--bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
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--device ${constraints_luts_device}
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COMMAND
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mv ${chipdb_dir}/chipdb.bba ${chipdb_bba}
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DEPENDS
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${constraints_luts_device}
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)
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add_custom_target(chipdb-${part}-bba DEPENDS ${chipdb_bba})
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add_dependencies(chipdb-${family}-bbas chipdb-${part}-bba)
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endfunction()
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set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
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file(MAKE_DIRECTORY ${chipdb_dir})
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add_custom_target(chipdb-${family}-bbas)
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add_subdirectory(${family}/examples/devices)
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@ -1,93 +0,0 @@
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#
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# nextpnr -- Next Generation Place and Route
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#
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# Copyright (C) 2021 Symbiflow Authors
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#
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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# This Makefile provides a streamlined way to create an example
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# FPGA interchange BBA suitable for placing and routing on Xilinx A35 parts.
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#
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# FPGA interchange device database is generated via RapidWright.
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#
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# Currently FPGA interchange physical netlist (e.g. place and route route) to
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# FASM support is not done, so bitstream generation relies on RapidWright to
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# convert FPGA interchange logical and physical netlist into a Vivado DCP.
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include ../common.mk
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.DELETE_ON_ERROR:
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.PHONY: all chipdb test debug_test
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all: chipdb
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build:
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mkdir build
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build/RapidWright: | build
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cd build && git clone https://github.com/Xilinx/RapidWright.git
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build/env: | build
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python3 -mvenv build/env
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build/python-fpga-interchange: | build
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cd build && git clone https://github.com/SymbiFlow/python-fpga-interchange.git
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build/fpga-interchange-schema: | build
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cd build && git clone https://github.com/SymbiFlow/fpga-interchange-schema.git
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build/.setup: | build/env build/fpga-interchange-schema build/python-fpga-interchange build/RapidWright
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source build/env/bin/activate && \
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cd build/python-fpga-interchange/ && \
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pip install -r requirements.txt
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touch build/.setup
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$(NEXTPNR_PATH)/build:
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mkdir $(NEXTPNR_PATH)/build
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$(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
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cd $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
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make -j -C $(NEXTPNR_PATH)/build
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build/nextpnr/fpga_interchange/chipdb.bba: build/.setup
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mkdir -p build/nextpnr/fpga_interchange
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source build/env/bin/activate && \
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cd build/python-fpga-interchange/ && \
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make \
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-f Makefile.rapidwright \
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NEXTPNR_PATH=$(realpath .)/build/nextpnr \
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RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
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INTERCHANGE_PATH=$(INTERCHANGE_PATH)
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$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm build/nextpnr/fpga_interchange/chipdb.bba
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$(NEXTPNR_PATH)/build/bba/bbasm -l build/nextpnr/fpga_interchange/chipdb.bba $(BBA_PATH)
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chipdb: $(BBA_PATH)
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test: chipdb
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$(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
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--chipdb $(BBA_PATH) \
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--package csg324 \
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--test
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debug_test: chipdb
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gdb --args $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
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--chipdb $(BBA_PATH) \
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--package csg324 \
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--test
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clean:
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rm -rf build
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@ -1,40 +0,0 @@
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## Makefile-driven BBA creation
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This Makefile will generate a Xilinx A35 chipdb if java, capnproto and
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capnproto-java are installed.
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### Installing dependencies
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Install java and javac if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install openjdk-10-jdk
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```
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Install capnproto if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install capnproto libcapnp-dev
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```
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Install capnproto-java if not already installed:
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```
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git clone https://github.com/capnproto/capnproto-java.git
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cd capnproto-java
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make
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sudo make install
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```
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### Instructions
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Once dependencies are installed, just run "make". This should download
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remaining dependencies and build the chipdb and build nextpnr if not built.
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#### Re-building the chipdb
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```
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# Remove the text BBA
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rm build/nextpnr/fpga_interchange/chipdb.bba
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# Build the BBA
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make
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```
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1
fpga_interchange/examples/devices/CMakeLists.txt
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1
fpga_interchange/examples/devices/CMakeLists.txt
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add_subdirectory(xc7a35t)
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2
fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
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2
fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
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generate_chipdb(part xc7a35tcsg324-1)
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generate_chipdb(part xc7a35tcpg236-1)
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@ -5,7 +5,14 @@ endif()
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find_package(ZLIB REQUIRED)
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find_package(ZLIB REQUIRED)
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set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
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# FIXME: Make patch data available in the python package and remove this cached var
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set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
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set(INTERCHANGE_SCHEMA_PATH $ENV{HOME}/fpga_interchange_schema CACHE PATH "Path to the FPGA interchange schema dir")
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add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
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add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
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include(${family}/examples/chipdb.cmake)
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include(${family}/examples/tests.cmake)
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foreach (target ${family_targets})
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foreach (target ${family_targets})
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target_include_directories(${target} PRIVATE ${TCL_INCLUDE_PATH})
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target_include_directories(${target} PRIVATE ${TCL_INCLUDE_PATH})
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