Improved log messages in SA placer, minor changes from clangformat
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
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2603c6d805
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d7f424b809
@ -146,7 +146,8 @@ static float get_wirelength(Context *ctx, NetInfo *net)
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// Attempt a SA position swap, return true on success or false on failure
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// Attempt a SA position swap, return true on success or false on failure
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static bool try_swap_position(Context *ctx, CellInfo *cell, BelId newBel, SAState &state)
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static bool try_swap_position(Context *ctx, CellInfo *cell, BelId newBel,
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SAState &state)
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{
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{
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static std::unordered_set<NetInfo *> update;
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static std::unordered_set<NetInfo *> update;
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static std::vector<std::pair<NetInfo *, float>> new_lengths;
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static std::vector<std::pair<NetInfo *, float>> new_lengths;
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@ -237,8 +238,10 @@ BelId random_bel_for_cell(Context *ctx, CellInfo *cell, SAState &state)
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int x = 0, y = 0;
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int x = 0, y = 0;
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ctx->estimatePosition(cell->bel, x, y);
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ctx->estimatePosition(cell->bel, x, y);
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while (true) {
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while (true) {
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int nx = ctx->rng(2 * state.diameter + 1) + std::max(x - state.diameter, 0);
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int nx = ctx->rng(2 * state.diameter + 1) +
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int ny = ctx->rng(2 * state.diameter + 1) + std::max(y - state.diameter, 0);
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std::max(x - state.diameter, 0);
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int ny = ctx->rng(2 * state.diameter + 1) +
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std::max(y - state.diameter, 0);
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int beltype_idx = state.bel_types.at(targetType);
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int beltype_idx = state.bel_types.at(targetType);
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if (nx >= int(state.fast_bels.at(beltype_idx).size()))
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if (nx >= int(state.fast_bels.at(beltype_idx).size()))
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continue;
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continue;
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@ -289,9 +292,10 @@ bool place_design_sa(Context *ctx)
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visit_cells.push(cell);
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visit_cells.push(cell);
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}
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}
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}
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}
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log_info("place_constraints placed %d\n", int(placed_cells));
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log_info("Placed %d cells based on constraints.\n", int(placed_cells));
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std::vector<CellInfo *> autoplaced;
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// Sort to-place cells for deterministic initial placement
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// Sort to-place cells for deterministic initial placement
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std::vector<CellInfo *> autoplaced;
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for (auto cell : ctx->cells) {
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for (auto cell : ctx->cells) {
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CellInfo *ci = cell.second;
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CellInfo *ci = cell.second;
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if (ci->bel == BelId()) {
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if (ci->bel == BelId()) {
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@ -300,11 +304,18 @@ bool place_design_sa(Context *ctx)
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}
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}
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std::sort(autoplaced.begin(), autoplaced.end(),
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std::sort(autoplaced.begin(), autoplaced.end(),
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[](CellInfo *a, CellInfo *b) { return a->name < b->name; });
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[](CellInfo *a, CellInfo *b) { return a->name < b->name; });
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ctx->shuffle(autoplaced);
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// Place cells randomly initially
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// Place cells randomly initially
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log_info("Creating initial placement for remaining %d cells.\n",
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int(autoplaced.size()));
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for (auto cell : autoplaced) {
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for (auto cell : autoplaced) {
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place_initial(ctx, cell);
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place_initial(ctx, cell);
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placed_cells++;
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placed_cells++;
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}
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}
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log_info("Running simulated annealing placer.\n");
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// Build up a fast position/type to Bel lookup table
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// Build up a fast position/type to Bel lookup table
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int max_x = 0, max_y = 0;
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int max_x = 0, max_y = 0;
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int bel_types = 0;
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int bel_types = 0;
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@ -330,6 +341,7 @@ bool place_design_sa(Context *ctx)
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state.fast_bels.at(type_idx).at(x).at(y).push_back(bel);
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state.fast_bels.at(type_idx).at(x).at(y).push_back(bel);
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}
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}
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state.diameter = std::max(max_x, max_y) + 1;
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state.diameter = std::max(max_x, max_y) + 1;
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// Calculate wirelength after initial placement
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// Calculate wirelength after initial placement
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state.curr_wirelength = 0;
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state.curr_wirelength = 0;
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for (auto net : ctx->nets) {
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for (auto net : ctx->nets) {
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@ -347,8 +359,8 @@ bool place_design_sa(Context *ctx)
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state.n_move = state.n_accept = 0;
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state.n_move = state.n_accept = 0;
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state.improved = false;
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state.improved = false;
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if (iter % 5 == 0)
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if (iter % 5 == 0 || iter == 1)
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log(" at iteration #%d: temp = %f, wire length = %f\n", iter,
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log_info(" at iteration #%d: temp = %f, wire length = %f\n", iter,
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state.temp, state.curr_wirelength);
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state.temp, state.curr_wirelength);
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for (int m = 0; m < 15; ++m) {
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for (int m = 0; m < 15; ++m) {
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@ -369,8 +381,12 @@ bool place_design_sa(Context *ctx)
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} else
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} else
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++n_no_progress;
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++n_no_progress;
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if (state.temp <= 1e-3 && n_no_progress >= 5)
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if (state.temp <= 1e-3 && n_no_progress >= 5) {
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if (iter % 5 != 0)
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log_info(" at iteration #%d: temp = %f, wire length = %f\n",
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iter, state.temp, state.curr_wirelength);
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break;
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break;
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}
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double Raccept = (double)state.n_accept / (double)state.n_move;
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double Raccept = (double)state.n_accept / (double)state.n_move;
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@ -211,7 +211,8 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio)
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replace_port(tbuf, "E", sbio, "OUTPUT_ENABLE");
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replace_port(tbuf, "E", sbio, "OUTPUT_ENABLE");
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ctx->nets.erase(donet->name);
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ctx->nets.erase(donet->name);
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if (!donet->users.empty())
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if (!donet->users.empty())
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log_error("unsupported tristate IO pattern for IO buffer '%s', "
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log_error(
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"unsupported tristate IO pattern for IO buffer '%s', "
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"instantiate SB_IO manually to ensure correct behaviour\n",
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"instantiate SB_IO manually to ensure correct behaviour\n",
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nxio->name.c_str(ctx));
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nxio->name.c_str(ctx));
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ctx->cells.erase(tbuf->name);
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ctx->cells.erase(tbuf->name);
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