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Add hierarchy to bel/wire/pip names

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-13 14:53:44 +02:00
parent 9374ef29bf
commit d80e60cce2
4 changed files with 31 additions and 19 deletions
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5
gui/mainwindow.cc
View File

@ -258,11 +258,12 @@ void MainWindow::prepareMenu(const QPoint &pos)
menu.exec(tree->mapToGlobal(pos));
}
void MainWindow::selectObject(QTreeWidgetItem *item)
void MainWindow::selectObject(QTreeWidgetItem *item)
{
ui->plainTextEdit->moveCursor(QTextCursor::End);
ui->plainTextEdit->insertPlainText(
std::string("selected " + item->text(0).toStdString() + "\n").c_str());
std::string("selected " + item->text(0).toStdString() + "\n")
.c_str());
ui->plainTextEdit->moveCursor(QTextCursor::End);
}

22
ice40/chip.cc
View File

@ -17,7 +17,8 @@
*
*/
#include <math.h>
#include <algorithm>
#include <cmath>
#include "log.h"
#include "nextpnr.h"
@ -239,6 +240,25 @@ PipId Chip::getPipByName(IdString name) const
return ret;
}
IdString Chip::getPipName(PipId pip) const
{
assert(pip != PipId());
int x = chip_info.pip_data[pip.index].x;
int y = chip_info.pip_data[pip.index].y;
std::string src_name =
chip_info.wire_data[chip_info.pip_data[pip.index].src].name;
std::replace(src_name.begin(), src_name.end(), '/', '.');
std::string dst_name =
chip_info.wire_data[chip_info.pip_data[pip.index].dst].name;
std::replace(dst_name.begin(), dst_name.end(), '/', '.');
return "X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name +
".->." + dst_name;
}
// -----------------------------------------------------------------------
BelId Chip::getPackagePinBel(const std::string &pin) const

11
ice40/chip.h
View File

@ -591,16 +591,7 @@ struct Chip
// -------------------------------------------------
PipId getPipByName(IdString name) const;
IdString getPipName(PipId pip) const
{
assert(pip != PipId());
std::string src_name =
chip_info.wire_data[chip_info.pip_data[pip.index].src].name;
std::string dst_name =
chip_info.wire_data[chip_info.pip_data[pip.index].dst].name;
return src_name + "->" + dst_name;
}
IdString getPipName(PipId pip) const;
void bindPip(PipId pip, IdString net)
{

12
ice40/chipdb.py
View File

@ -187,7 +187,7 @@ def add_bel_output(bel, wire, port):
def add_bel_lc(x, y, z):
bel = len(bel_name)
bel_name.append("%d_%d_lc%d" % (x, y, z))
bel_name.append("X%d/Y%d/lc%d" % (x, y, z))
bel_type.append("ICESTORM_LC")
bel_pos.append((x, y, z))
bel_wires.append(list())
@ -227,7 +227,7 @@ def add_bel_lc(x, y, z):
def add_bel_io(x, y, z):
bel = len(bel_name)
bel_name.append("%d_%d_io%d" % (x, y, z))
bel_name.append("X%d/Y%d/io%d" % (x, y, z))
bel_type.append("SB_IO")
bel_pos.append((x, y, z))
bel_wires.append(list())
@ -257,7 +257,7 @@ def add_bel_io(x, y, z):
def add_bel_ram(x, y):
bel = len(bel_name)
bel_name.append("%d_%d_ram" % (x, y))
bel_name.append("X%d/Y%d/ram" % (x, y))
bel_type.append("ICESTORM_RAM")
bel_pos.append((x, y, 0))
bel_wires.append(list())
@ -288,7 +288,7 @@ def add_bel_ram(x, y):
def add_bel_gb(x, y, g):
bel = len(bel_name)
bel_name.append("%d_%d_gb" % (x, y))
bel_name.append("X%d/Y%d/gb" % (x, y))
bel_type.append("SB_GB")
bel_pos.append((x, y, 0))
bel_wires.append(list())
@ -384,7 +384,7 @@ for wire in range(num_wires):
num_bels_downhill = 0
info = " {"
info += "\"%d_%d_%s\", " % wire_names_r[wire]
info += "\"X%d/Y%d/%s\", " % wire_names_r[wire]
info += "%d, %d, %s, %s, %d, " % (num_uphill, num_downhill, list_uphill, list_downhill, num_bels_downhill)
if wire in wire_uphill_belport:
@ -414,7 +414,7 @@ for package in packages:
pins_info = []
for pin in pins:
pinname, x, y, z = pin
pin_bel = "%d_%d_io%d" % (x, y, z)
pin_bel = "X%d/Y%d/io%d" % (x, y, z)
bel_idx = bel_name.index(pin_bel)
pins_info.append('{"%s", %d}' % (pinname, bel_idx))
print("static PackagePinPOD package_%s_pins[%d] = {" % (safename, len(pins_info)))